# AD5624BRMZ-REEL7

**Analog Devices** · Digital To Analog Converters (DAC) · MSOP-10

AD5624BRMZ-REEL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A, and the output amplifier has rail-to-rail operation. |
| 2 | VOUTB | output | Analog output voltage from DAC B, and the output amplifier has rail-to-rail operation. |
| 3 | GND | power_in | Ground reference point for all circuitry on the device. |
| 4 | VOUTC | output | Analog output voltage from DAC C, and the output amplifier has rail-to-rail operation. |
| 5 | VOUTD | output | Analog output voltage from DAC D, and the output amplifier has rail-to-rail operation. |
| 6 | SYNC | input | Active-low frame synchronization input: when SYNC goes low, the SCLK and DIN buffers power on and 24 falling clock edges are read in, and a rising SYNC edge before the 24th falling edge is treated as an interrupt that causes the write to be ignored. |
| 7 | SCLK | input | Serial clock input; data is clocked into the input shift register on its falling edge at rates up to 50 MHz. |
| 8 | DIN | input | Serial data input to the 24-bit input shift register, clocked in on the falling edge of SCLK. |
| 9 | VDD | power_in | Power supply input that can be operated from 2.7 V to 5.5 V, decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. |
| 10 | VREF | power_in | Reference voltage input that the device requires to set the DAC output range. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Acquisition |
| Pins | 10 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDD) | VDD | 2.7 |  | 5.5 | V |  | 4 |
| Operating Temperature Range (Industrial, B Grade) | TA | -40 |  | 105 | °C |  | 6 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 6 |
| Junction Temperature (TJ max) | TJ |  |  | 150 | °C |  | 6 |
| VDD to GND | VDD | -0.3 |  | 7 | V | TA = 25°C | 6 |
| θJA Thermal Impedance, MSOP package (4-layer board) | θJA |  | 142 |  | °C/W | MSOP package, 4-layer board | 6 |
| θJC Thermal Impedance, MSOP package | θJC |  | 43.7 |  | °C/W |  | 6 |
| Zero Code Error |  |  | 2 | 10 | mV | All zeroes loaded to DAC register | 3 |
| Offset Error |  | -10 | 1 | 10 | mV |  | 3 |
| Full-Scale Error |  | -1 | -0.1 | 1 | % of FSR | All ones loaded to DAC register | 3 |
| Gain Error |  | -1.5 |  | 1.5 | % of FSR |  | 3 |
| Zero Code Error Drift |  | -2 |  | 2 | μV/°C |  | 3 |
| Gain Temperature Coefficient |  | -2.5 |  | 2.5 | ppm Of FSR/°C |  | 3 |
| Relative Accuracy (INL) |  | -1 | 0.5 | 1 | LSB |  | 3 |
| Reference Current |  |  | 170 | 200 | μA | VREF = VDD = 5.5 V | 3 |
| Input Current |  | -2 |  | 2 | μA | All digital inputs | 3 |
| Input Low Voltage | VINL |  |  | 0.8 | V | VDD = 5 V, 3 V | 3 |
| Input High Voltage | VINH | 2 |  |  | V | VDD = 5 V, 3 V | 3 |
| IDD (Normal Mode) | IDD |  | 0.45 | 0.9 | mA | VIH = VDD, VIL = GND; VDD = 4.5 V to 5.5 V | 4 |
| IDD (Normal Mode) | IDD |  | 0.44 | 0.85 | mA | VIH = VDD, VIL = GND; VDD = 2.7 V to 3.6 V | 4 |
| IDD (All Power-Down Modes) | IDD |  | 0.48 | 1 | μA | VIH = VDD, VIL = GND; VDD = 4.5 V to 5.5 V | 4 |
| IDD (All Power-Down Modes) | IDD |  | 0.2 | 1 | μA | VIH = VDD, VIL = GND; VDD = 2.7 V to 3.6 V | 4 |
| Output Voltage Settling Time (AD5624) |  |  | 3 | 4.5 | μs | ¼ to ¾ scale settling to ±0.5 LSB | 4 |
| SCLK cycle time (t1) | t1 | 20 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| SCLK high time (t2) | t2 | 9 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| SCLK low time (t3) | t3 | 9 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| SYNC to SCLK falling edge setup time (t4) | t4 | 13 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| Data setup time (t5) | t5 | 5 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| Data hold time (t6) | t6 | 5 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| SCLK falling edge to SYNC rising edge (t7) | t7 | 0 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| Minimum SYNC high time (t8) | t8 | 15 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| SYNC rising edge to SCLK fall ignore (t9) | t9 | 13 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |
| SCLK falling edge to SYNC fall ignore (t10) | t10 | 0 |  |  | ns | VDD = 2.7 V to 5.5 V | 5 |

## CAD (KiCad official)

- Symbol: `AD5624BRMZ-REEL7`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `ad5624brmz-reel7-etched.step` / `ad5624brmz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5624brmz-reel7.step` / `ad5624brmz-reel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589801193280479232) (23 pp, sha256 `b0e482512cefce40`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5624brmz-reel7-datasheet.pdf)