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Ray Set visibility: public 790372e 3d ago
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{
  "schema_version": 1,
  "type": "component",
  "slug": "ad5623rbrmz-5",
  "title": "AD5623RBRMZ-5",
  "brief": "Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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  "component": {
    "mpn": "AD5623RBRMZ-5",
    "manufacturer": "Analog Devices",
    "package": "MSOP-10",
    "pin_count": 10,
    "category": "Data Converters",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5623R_43R_63R.pdf",
    "parts": {
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      "footprint": "ad5623rbrmz-5.kicad_mod",
      "model_3d": "ad5623rbrmz-5-hero.glb",
      "model_3d_plain": "ad5623rbrmz-5-etched.glb",
      "model_3d_step": "ad5623rbrmz-5-etched.step",
      "model_3d_step_plain": "ad5623rbrmz-5.step",
      "lbr": "ad5623rbrmz-5.lbr"
    },
    "distributor_links": {
      "lcsc": "C578237",
      "digikey": "505-AD5623RBRMZ-5-ND",
      "mouser": "584-AD5623RBRMZ-5"
    },
    "distributor_check": {
      "checked_at": "2026-11-02T16:49:11Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
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      "mouser": {
        "pn": "584-AD5623RBRMZ-5",
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    },
    "pins": [
      {
        "number": "1",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "2",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC B; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground, the reference point for all circuitry on the part."
      },
      {
        "number": "4",
        "name": "LDAC",
        "type": "input",
        "description": "Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, enabling simultaneous update of all DAC outputs, or it can be tied permanently low."
      },
      {
        "number": "5",
        "name": "CLR",
        "type": "input",
        "description": "Asynchronous, falling-edge-sensitive clear input that loads zero scale to all input and DAC registers, clearing the output to 0 V, and is ignored by LDAC pulses while low."
      },
      {
        "number": "6",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low, level-triggered frame synchronization input that enables the input shift register, with the DAC updated after the 24th clock cycle unless SYNC is taken high first."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input on whose falling edge data is clocked into the input shift register, with transfer rates up to 50 MHz."
      },
      {
        "number": "8",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to the 24-bit shift register, clocked in on the falling edge of the serial clock."
      },
      {
        "number": "9",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
      },
      {
        "number": "10",
        "name": "VREFIN/VREFOUT",
        "type": "bidirectional",
        "description": "Common reference input/output that is the reference output when the internal reference is selected and the reference input when an external reference is used, defaulting to reference input."
      }
    ],
    "provenance": {
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        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 9,
        "cost_usd": 0.013,
        "at": "2026-11-02T16:49:01"
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        "pages": 32,
        "sha256": "f5a235479cd9f402",
        "source_tier": "mfr"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 10,
        "described": 10,
        "cites_pages": true,
        "refuses_to_fabricate": true
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    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "MSOP-10",
      "Category": "Data Converters",
      "Pins": "10"
    },
    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "datasheet_sha256": "f5a235479cd9f4025fa0aa40a39a7a0e3456364943986b92714e47af6eada51b",
      "rows": [
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          "kind": "tolerance",
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          "max": 1,
          "conditions": "B grade, AD5623R, VDD = 4.5 V to 5.5 V",
          "source_page": 4,
          "source": "datasheet"
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        {
          "name": "SCLK falling edge to SYNC rising edge",
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        {
          "name": "Minimum SYNC high time",
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          "name": "Operating Temperature Range (Industrial)",
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        {
          "name": "Storage Temperature Range",
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