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AD5623RBRMZ-5

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Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified AD5623RBRMZ-5

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5623RBRMZ-5 · MSOP-10 · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C578237, digikey 505-AD5623RBRMZ-5-ND, mouser 584-AD5623RBRMZ-5
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zpbu0hs1/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5623rbrmz-5.kicad_sym✓ ad5623rbrmz-5.kicad_mod✓ ad5623rbrmz-5.step
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AD5623RBRMZ-5

Analog Devices · Digital To Analog Converters (DACs) · MSOP-10

AD5623RBRMZ-5 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A; the output amplifier has rail-to-rail operation.
2 VOUTB output Analog output voltage from DAC B; the output amplifier has rail-to-rail operation.
3 GND power_in Ground, the reference point for all circuitry on the part.
4 LDAC input Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, enabling simultaneous update of all DAC outputs, or it can be tied permanently low.
5 CLR input Asynchronous, falling-edge-sensitive clear input that loads zero scale to all input and DAC registers, clearing the output to 0 V, and is ignored by LDAC pulses while low.
6 SYNC input Active-low, level-triggered frame synchronization input that enables the input shift register, with the DAC updated after the 24th clock cycle unless SYNC is taken high first.
7 SCLK input Serial clock input on whose falling edge data is clocked into the input shift register, with transfer rates up to 50 MHz.
8 DIN input Serial data input to the 24-bit shift register, clocked in on the falling edge of the serial clock.
9 VDD power_in Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
10 VREFIN/VREFOUT bidirectional Common reference input/output that is the reference output when the internal reference is selected and the reference input when an external reference is used, defaulting to reference input.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category Data Converters
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL) -1 1 LSB B grade, AD5623R, VDD = 4.5 V to 5.5 V 4
Differential Nonlinearity -0.25 0.25 LSB B grade, AD5623R, guaranteed monotonic by design 4
Zero-Scale Error 2 10 mV B grade, all 0s loaded to DAC register 4
Offset Error -10 10 mV B grade 4
Full-Scale Error -1 -0.1 1 % of FSR B grade, all 1s loaded to DAC register 4
Gain Error -1.5 1.5 % of FSR 4
Zero-Scale Error Drift -2 2 µV/°C 4
Gain Temperature Coefficient -2.5 2.5 ppm of FSR/°C 4
Output Voltage Range VOUT 0 V upper limit printed as VDD 4
Reference Current 170 200 µA VREF = VDD = 5.5 V 4
Reference Input Range VREF 0.75 V upper limit printed as VDD 4
Reference Output Voltage VREFOUT 2.495 2.505 V At ambient 5
Reference Temperature Coefficient -5 5 ppm/°C MSOP package models 5
Input Current -2 2 µA All digital inputs 5
Input Low Voltage VINL 0.8 V VDD = 5 V 5
Input High Voltage VINH 2 V VDD = 5 V 5
Supply Voltage VDD 4.5 5.5 V B grade 5
Normal Mode Supply Current, internal reference off IDD 0.25 0.45 mA VIH = VDD and VIL = GND, VDD = 4.5 V to 5.5 V 5
Normal Mode Supply Current, internal reference on IDD 0.8 1 mA VIH = VDD and VIL = GND, VDD = 4.5 V to 5.5 V 5
Power-Down Mode Supply Current IDD 0.48 1 µA VIH = VDD and VIL = GND, VDD = 4.5 V to 5.5 V 5
Output Voltage Settling Time 3 4.5 µs AD5623R, ¼ to ¾ scale settling to ±0.5 LSB 7
SCLK cycle time t1 20 ns VDD = 2.7 V to 5.5 V 8
SCLK high time t2 9 ns VDD = 2.7 V to 5.5 V 8
SCLK low time t3 9 ns VDD = 2.7 V to 5.5 V 8
SYNC to SCLK falling edge setup time t4 13 ns VDD = 2.7 V to 5.5 V 8
Data setup time t5 5 ns VDD = 2.7 V to 5.5 V 8
Data hold time t6 5 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V 8
Minimum SYNC high time t8 15 ns VDD = 2.7 V to 5.5 V 8
SYNC rising edge to SCLK fall ignore t9 13 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC fall ignore t10 0 ns VDD = 2.7 V to 5.5 V 8
LDAC pulse width low t11 10 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC rising edge t12 15 ns VDD = 2.7 V to 5.5 V 8
CLR pulse width low t13 5 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC falling edge t14 0 ns VDD = 2.7 V to 5.5 V 8
CLR pulse activation time t15 300 ns VDD = 2.7 V to 5.5 V 8
VDD to GND VDD -0.3 7 V TA = 25°C 9
VOUT to GND VOUT -0.3 V upper limit printed as VDD + 0.3 V; TA = 25°C 9
VREFIN/VREFOUT to GND VREFIN/VREFOUT -0.3 V upper limit printed as VDD + 0.3 V; TA = 25°C 9
Digital Input Voltage to GND -0.3 V upper limit printed as VDD + 0.3 V; TA = 25°C 9
Operating Temperature Range (Industrial) TA -40 105 °C 9
Storage Temperature Range -65 150 °C 9
Junction Temperature (TJ max) TJ 150 °C 9
Reflow Soldering Peak Temperature, Pb-Free 260 °C printed as 260(+0/−5)°C 9
MSOP Package Thermal Impedance, 4-Layer Board θJA 142 °C/W 9
MSOP Package Thermal Impedance, junction to case θJC 43.7 °C/W 9

CAD (KiCad official)

  • Symbol: AD5623RBRMZ-5
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5623rbrmz-5-etched.step / ad5623rbrmz-5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5623rbrmz-5.step / ad5623rbrmz-5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 f5a235479cd9f402, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF