AD5623RBRMZ-3REEL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUTA	output	Analog output voltage from DAC A with rail-to-rail output amplifier operation.
2	VOUTB	output	Analog output voltage from DAC B with rail-to-rail output amplifier operation.
3	GND	power_in	Ground reference point for all circuitry on the part.
4	LDAC	input	Pulsing this pin low updates any or all DAC registers if the input registers have new data, allowing simultaneous update of all DAC outputs, or it can be tied permanently low.
5	CLR	input	Falling-edge-sensitive asynchronous clear input that ignores LDAC pulses while low and loads zero scale to all input and DAC registers, clearing the output to 0 V.
6	SYNC	input	Active-low level-triggered frame synchronization input that enables the input shift register when low, with the DAC updated after the 24th clock unless SYNC is taken high before that edge.
7	SCLK	input	Serial clock input that clocks data into the input shift register on the falling edge at rates up to 50 MHz.
8	DIN	input	Serial data input to the 24-bit shift register, clocked in on the falling edge of the serial clock.
9	VDD	power_in	Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
10	VREFIN/VREFOUT	bidirectional	Common reference input/output that is the reference output when the internal reference is selected and the reference input when using an external reference (default is input).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-10
Category	Communication Interface Chip/UART/485/232
Pins	10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy (AD5623R)	INL	-1	0.5	1	LSB	B grade, VDD = 2.7 V to 3.6 V	6
Zero-Scale Error			2	10	mV	All 0s loaded to DAC register	6
Offset Error		-10	1	10	mV		6
Full-Scale Error		-1	-0.1	1	% of FSR	All 1s loaded to DAC register	6
Reference Current			170	200	µA	VREF = VDD = 3.6 V	6
Reference Input Range		0.75			V	Max is VDD	6
Reference Output Voltage		1.247		1.253	V	At ambient	6
Reference Temperature Coefficient			5	15	ppm/°C	MSOP package models	6
Input Low Voltage	VINL			0.8	V	VDD = 3 V	7
Input High Voltage	VINH	2			V	VDD = 3 V	7
Digital Input Current		-2		2	µA	All digital inputs	7
Supply Voltage	VDD	2.7		3.6	V		7
IDD Normal Mode, internal reference off	IDD		200	425	µA	VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; internal reference off	7
IDD Normal Mode, internal reference on	IDD		800	900	µA	VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; internal reference on	7
IDD All Power-Down Modes	IDD		0.2	1	µA	VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND	7
Output Voltage Settling Time (AD5623R)			3	4.5	µs	¼ to ¾ scale settling to ±0.5 LSB	7
Differential Nonlinearity (AD5623R)	DNL		0.25		LSB	Guaranteed monotonic by design	6
Gain Error			1.5		% of FSR		6
Zero-Scale Error Drift			2		µV/°C		6
Gain Temperature Coefficient			2.5		ppm Of FSR/°C		6
DC Power Supply Rejection Ratio	PSRR		-100		dB	DAC code = midscale; VDD = 3 V ± 10%	6
DC Output Impedance			0.5		Ω		6
Short Circuit Current			30		mA	VDD = 3 V	6
Power-Up Time			4		µs	Coming out of power-down mode; VDD = 3 V	6
Reference Input Impedance			26		kΩ		6
Reference Output Impedance			7.5		kΩ		6
Slew Rate			1.8		V/µs		7
Output Noise			15		µV p-p	0.1 Hz to 10 Hz	7
SCLK cycle time	t1	20			ns	VDD = 2.7 V to 5.5 V	8
SCLK high time	t2	9			ns	VDD = 2.7 V to 5.5 V	8
SCLK low time	t3	9			ns	VDD = 2.7 V to 5.5 V	8
SYNC to SCLK falling edge setup time	t4	13			ns	VDD = 2.7 V to 5.5 V	8
Data setup time	t5	5			ns	VDD = 2.7 V to 5.5 V	8
Data hold time	t6	5			ns	VDD = 2.7 V to 5.5 V	8
SCLK falling edge to SYNC rising edge	t7	0			ns	VDD = 2.7 V to 5.5 V	8
Minimum SYNC high time	t8	15			ns	VDD = 2.7 V to 5.5 V	8
CLR pulse activation time	t15			300	ns	VDD = 2.7 V to 5.5 V	8
VDD to GND	VDD	-0.3		7	V	TA = 25°C	9
VOUT to GND	VOUT	-0.3			V	Max is VDD + 0.3 V	9
Digital Input Voltage to GND		-0.3			V	Max is VDD + 0.3 V	9
Operating Temperature Range (Industrial)		-40		105	°C		9
Storage Temperature Range		-65		150	°C		9
Junction Temperature	TJ max			150	°C		9
Thermal Impedance, MSOP	θJA		142		°C/W	MSOP package, 4-layer board	9
Thermal Impedance, MSOP	θJC		43.7		°C/W	MSOP package, 4-layer board	9

CAD (KiCad official)

Symbol: AD5623RBRMZ-3REEL7
Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
3D model: MSOP-10 (KiCad packages3D, STEP)
3D model files: ad5623rbrmz-3reel7-etched.step / ad5623rbrmz-3reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5623rbrmz-3reel7.step / ad5623rbrmz-3reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (32 pp, sha256 f5a235479cd9f402, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5623RBRMZ-3REEL7

Verified AD5623RBRMZ-3REEL7

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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