component
AD5623RBRMZ-3
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD5623RBRMZ-3
Analog Devices · Digital To Analog Converters (DACs) · MSOP-10
AD5623RBRMZ-3 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A; the output amplifier has rail-to-rail operation. |
| 2 | VOUTB | output | Analog output voltage from DAC B; the output amplifier has rail-to-rail operation. |
| 3 | GND | power_in | Ground reference point for all circuitry on the part. |
| 4 | LDAC | input | Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, or it can be tied permanently low. |
| 5 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads zero scale to all input and DAC registers, clearing the output to 0 V, and all LDAC pulses are ignored while CLR is low. |
| 6 | SYNC | input | Level-triggered active-low frame synchronization input; the DAC updates following the 24th clock cycle unless SYNC is taken high before this edge. |
| 7 | SCLK | input | Serial clock input from which data is clocked into the input shift register on the falling edge, at rates up to 50 MHz. |
| 8 | DIN | input | Serial data input to a 24-bit shift register, with data clocked in on the falling edge of the serial clock. |
| 9 | VDD | power_in | Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 10 | VREFIN/VREFOUT | bidirectional | Reference output when the internal reference is selected and reference input when an external reference is used; the default for this pin is a reference input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | 0.5 | 1 | LSB | 6 | |||
| Differential Nonlinearity | 0.25 | LSB | Guaranteed monotonic by design | 6 | |||
| Zero-Scale Error | 2 | 10 | mV | All 0s loaded to DAC register | 6 | ||
| Offset Error | 1 | 10 | mV | 6 | |||
| Full-Scale Error | -0.1 | 1 | % of FSR | All 1s loaded to DAC register | 6 | ||
| Gain Error | 1.5 | % of FSR | 6 | ||||
| Zero-Scale Error Drift | 2 | µV/°C | 6 | ||||
| Gain Temperature Coefficient | 2.5 | ppm Of FSR/°C | 6 | ||||
| DC Power Supply Rejection Ratio | -100 | dB | DAC code = midscale; VDD = 3 V ± 10% | 6 | |||
| DC Crosstalk (External Reference) due to full-scale output change | 10 | µV | Due to full-scale output change; RL = 2 kΩ to GND or VDD | 6 | |||
| DC Crosstalk (Internal Reference) due to full-scale output change | 25 | µV | Due to full-scale output change; RL = 2 kΩ to GND or VDD | 6 | |||
| Output Voltage Range | VOUT | 0 | V | 6 | |||
| Capacitive Load Stability | 2 | nF | RL = ∞ | 6 | |||
| Capacitive Load Stability | 10 | nF | RL = 2 kΩ | 6 | |||
| DC Output Impedance | 0.5 | Ω | 6 | ||||
| Reference Current | 170 | 200 | µA | VREF = VDD = 3.6 V | 6 | ||
| Reference Output Voltage | 1.247 | 1.253 | V | At ambient | 6 | ||
| Reference Temperature Coefficient | 5 | 15 | ppm/°C | MSOP package models | 6 | ||
| Input Current | -2 | 2 | µA | All digital inputs | 7 | ||
| Input Low Voltage | VINL | 0.8 | V | VDD = 3 V | 7 | ||
| Input High Voltage | VINH | 2 | V | VDD = 3 V | 7 | ||
| Pin Capacitance | 3 | pF | DIN, SCLK, and SYNC | 7 | |||
| Supply Voltage | VDD | 2.7 | 3.6 | V | 7 | ||
| IDD (Normal Mode) | IDD | 200 | 425 | µA | VDD = 2.7 V to 3.6 V; Internal reference off | 7 | |
| IDD (Normal Mode) | IDD | 800 | 900 | µA | VDD = 2.7 V to 3.6 V; Internal reference on | 7 | |
| IDD (All Power-Down Modes) | IDD | 0.2 | 1 | µA | VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND | 7 | |
| Output Voltage Settling Time (AD5623R) | 3 | 4.5 | µs | ¼ to ¾ scale settling to ±0.5 LSB | 7 | ||
| Slew Rate | 1.8 | V/µs | 7 | ||||
| Multiplying Bandwidth | 340 | kHz | VREF = 2 V ± 0.1 V p-p | 7 | |||
| Total Harmonic Distortion | -80 | dB | VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz | 7 | |||
| Output Noise Spectral Density | 120 | nV/√Hz | DAC code = midscale, 1 kHz | 7 | |||
| Output Noise Spectral Density | 100 | nV/√Hz | DAC code = midscale, 10 kHz | 7 | |||
| Output Noise | 15 | μV p-p | 0.1 Hz to 10 Hz | 7 | |||
| SCLK cycle time | t1 | 20 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SCLK high time | t2 | 9 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SCLK low time | t3 | 9 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SYNC to SCLK falling edge setup time | t4 | 13 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| Data setup time | t5 | 5 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| Data hold time | t6 | 5 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SCLK falling edge to SYNC rising edge | t7 | 0 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| Minimum SYNC high time | t8 | 15 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SYNC rising edge to SCLK fall ignore | t9 | 13 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SCLK falling edge to SYNC fall ignore | t10 | 0 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| LDAC pulse width low | t11 | 10 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SCLK falling edge to LDAC rising edge | t12 | 15 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| CLR pulse width low | t13 | 5 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| SCLK falling edge to LDAC falling edge | t14 | 0 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| CLR pulse activation time | t15 | 300 | ns | VDD = 2.7 V to 5.5 V | 8 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 9 | ||
| VOUT to GND | VOUT | -0.3 | V | 9 | |||
| VREFIN/VREFOUT to GND | VREFIN/VREFOUT | -0.3 | V | 9 | |||
| Digital Input Voltage to GND | -0.3 | V | 9 | ||||
| Operating Temperature Range (Industrial) | -40 | 105 | °C | 9 | |||
| Storage Temperature Range | -65 | 150 | °C | 9 | |||
| Junction Temperature (TJ max) | TJ | 150 | °C | 9 | |||
| θJA Thermal Impedance | θJA | 142 | °C/W | MSOP Package (4-Layer Board) | 9 | ||
| θJC Thermal Impedance | θJC | 43.7 | °C/W | MSOP Package (4-Layer Board) | 9 |
CAD (KiCad official)
- Symbol:
AD5623RBRMZ-3 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5623rbrmz-3-etched.step/ad5623rbrmz-3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5623rbrmz-3.step/ad5623rbrmz-3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
f5a235479cd9f402, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).