component
AD5611BKSZ-500RL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5611BKSZ-500RL7
Analog Devices · Digital To Analog Converters (DACs) · SC-70-6
AD5611BKSZ-500RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Active-low level-triggered frame synchronization input; when low it enables the input shift register, the DAC updates after the 16th clock unless SYNC is taken high before then, in which case the write is ignored. |
| 2 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 30 MHz. |
| 3 | SDIN | input | Serial data input to the 16-bit shift register, clocked in on the falling edge of the serial clock. |
| 4 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V; decouple VDD to GND. |
| 5 | GND | power_in | Ground reference point for all circuitry on the device. |
| 6 | VOUT | output | Analog output voltage from the DAC with rail-to-rail output amplifier operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | ADC/DAC/Data Conversion |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), AD5611 B grade | INL | -0.5 | 0.5 | LSB | VDD = 4.5 V to 5.5 V; RL = 2 kΩ; CL = 200 pF | 3 | |
| Differential Nonlinearity (DNL), AD5611 | DNL | -0.5 | 0.5 | LSB | Guaranteed monotonic by design | 3 | |
| Zero-Code Error | 0.5 | 10 | mV | All 0s loaded to DAC register | 3 | ||
| Offset Error | 0.063 | 10 | mV | 3 | |||
| Gain Error | 0.0004 | 0.037 | %FSR | 3 | |||
| Output Voltage Settling Time | 6 | 10 | µs | Code ¼ scale to ¾ scale | 3 | ||
| Input Current | -2 | 2 | µA | Total current flowing into all pins | 3 | ||
| Input High Voltage | VINH | 1.8 | V | VDD = 4.7 V to 5.5 V | 3 | ||
| Input High Voltage | VINH | 1.4 | V | VDD = 2.7 V to 3.6 V | 3 | ||
| Input Low Voltage | VINL | 0.8 | V | VDD = 4.7 V to 5.5 V | 3 | ||
| Input Low Voltage | VINL | 0.6 | V | VDD = 2.7 V to 3.6 V | 3 | ||
| Supply Voltage | VDD | 2.7 | 5.5 | V | All digital inputs at 0 V or VDD | 4 | |
| IDD Normal Mode | IDD | 75 | 100 | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 4 | |
| IDD Normal Mode | IDD | 60 | 90 | µA | VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 4 | |
| IDD All Power-Down Modes | IDD | 0.5 | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 4 | ||
| IDD All Power-Down Modes | IDD | 0.2 | µA | VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND | 4 | ||
| SCLK cycle time | t1 | 33 | ns | SCLK cycle time | 4 | ||
| SCLK high time | t2 | 5 | ns | SCLK high time | 4 | ||
| SCLK low time | t3 | 5 | ns | SCLK low time | 4 | ||
| SYNC to SCLK falling edge setup time | t4 | 10 | ns | SYNC to SCLK falling edge setup time | 4 | ||
| Data setup time | t5 | 5 | ns | Data setup time | 4 | ||
| Data hold time | t6 | 4.5 | ns | Data hold time | 4 | ||
| SCLK falling edge to SYNC rising edge | t7 | 0 | ns | SCLK falling edge to SYNC rising edge | 4 | ||
| Minimum SYNC high time | t8 | 20 | ns | Minimum SYNC high time | 4 | ||
| SYNC rising edge to next SCLK falling edge ignored | t9 | 13 | ns | SYNC rising edge to next SCLK falling edge ignored | 4 | ||
| VDD to GND | VDD | -0.3 | 7 | V | TA = 25°C | 5 | |
| Digital Input Voltage to GND | -0.3 | V | Max is VDD + 0.3 V | 5 | |||
| VOUT to GND | VOUT | -0.3 | V | Max is VDD + 0.3 V | 5 | ||
| Operating Temperature Range (Industrial A/B) | -40 | 125 | °C | 5 | |||
| Storage Temperature Range | -65 | 160 | °C | 5 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 5 | |||
| Lead Temperature, Vapor Phase | 215 | °C | 60 sec | 5 | |||
| Lead Temperature, Infrared | 220 | °C | 15 sec | 5 | |||
| ESD (Human Body Model) | 2 | kV | 5 | ||||
| θJA Thermal Impedance, SC70 | θJA | 433.34 | °C/W | SC70 Package | 5 | ||
| θJC Thermal Impedance, SC70 | θJC | 149.47 | °C/W | SC70 Package | 5 | ||
| Resolution | 10 | Bits | AD5611 | 3 | |||
| Full-Scale Error | 0.5 | mV | All 1s loaded to DAC register; printed as ±0.5 | 3 | |||
| Zero-Code Error Drift | 5 | µV/°C | 3 | ||||
| Gain Temperature Coefficient | 2 | ppm FSR/°C | 3 | ||||
| Slew Rate | 0.5 | V/µs | 3 | ||||
| Short-Circuit Current | 15 | mA | VDD = 3 V/5 V | 3 | |||
| DC Output Impedance | 0.5 | Ω | 3 | ||||
| Output Noise Spectral Density | 120 | nV/√Hz | DAC code = midscale, 1 kHz | 3 | |||
| Pin Input Capacitance | 3 | pF | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | ESD (Human Body Model) 2.0 kV Stresses at or above those listed under Absolute Maximum | 5 |
CAD (KiCad official)
- Symbol:
AD5611BKSZ-500RL7 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files:
ad5611bksz-500rl7-etched.step/ad5611bksz-500rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5611bksz-500rl7.step/ad5611bksz-500rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (21 pp, sha256
05bad4273b7f5318, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5611BKSZ-500RL7
**Analog Devices** · Digital To Analog Converters (DACs) · SC-70-6
AD5611BKSZ-500RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Active-low level-triggered frame synchronization input; when low it enables the input shift register, the DAC updates after the 16th clock unless SYNC is taken high before then, in which case the write is ignored. |
| 2 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 30 MHz. |
| 3 | SDIN | input | Serial data input to the 16-bit shift register, clocked in on the falling edge of the serial clock. |
| 4 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V; decouple VDD to GND. |
| 5 | GND | power_in | Ground reference point for all circuitry on the device. |
| 6 | VOUT | output | Analog output voltage from the DAC with rail-to-rail output amplifier operation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | ADC/DAC/Data Conversion |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), AD5611 B grade | INL | -0.5 | | 0.5 | LSB | VDD = 4.5 V to 5.5 V; RL = 2 kΩ; CL = 200 pF | 3 |
| Differential Nonlinearity (DNL), AD5611 | DNL | -0.5 | | 0.5 | LSB | Guaranteed monotonic by design | 3 |
| Zero-Code Error | | | 0.5 | 10 | mV | All 0s loaded to DAC register | 3 |
| Offset Error | | | 0.063 | 10 | mV | | 3 |
| Gain Error | | | 0.0004 | 0.037 | %FSR | | 3 |
| Output Voltage Settling Time | | | 6 | 10 | µs | Code ¼ scale to ¾ scale | 3 |
| Input Current | | -2 | | 2 | µA | Total current flowing into all pins | 3 |
| Input High Voltage | VINH | 1.8 | | | V | VDD = 4.7 V to 5.5 V | 3 |
| Input High Voltage | VINH | 1.4 | | | V | VDD = 2.7 V to 3.6 V | 3 |
| Input Low Voltage | VINL | | | 0.8 | V | VDD = 4.7 V to 5.5 V | 3 |
| Input Low Voltage | VINL | | | 0.6 | V | VDD = 2.7 V to 3.6 V | 3 |
| Supply Voltage | VDD | 2.7 | | 5.5 | V | All digital inputs at 0 V or VDD | 4 |
| IDD Normal Mode | IDD | | 75 | 100 | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 4 |
| IDD Normal Mode | IDD | | 60 | 90 | µA | VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; DAC active, excluding load current | 4 |
| IDD All Power-Down Modes | IDD | | 0.5 | | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 4 |
| IDD All Power-Down Modes | IDD | | 0.2 | | µA | VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND | 4 |
| SCLK cycle time | t1 | 33 | | | ns | SCLK cycle time | 4 |
| SCLK high time | t2 | 5 | | | ns | SCLK high time | 4 |
| SCLK low time | t3 | 5 | | | ns | SCLK low time | 4 |
| SYNC to SCLK falling edge setup time | t4 | 10 | | | ns | SYNC to SCLK falling edge setup time | 4 |
| Data setup time | t5 | 5 | | | ns | Data setup time | 4 |
| Data hold time | t6 | 4.5 | | | ns | Data hold time | 4 |
| SCLK falling edge to SYNC rising edge | t7 | 0 | | | ns | SCLK falling edge to SYNC rising edge | 4 |
| Minimum SYNC high time | t8 | 20 | | | ns | Minimum SYNC high time | 4 |
| SYNC rising edge to next SCLK falling edge ignored | t9 | 13 | | | ns | SYNC rising edge to next SCLK falling edge ignored | 4 |
| VDD to GND | VDD | -0.3 | | 7 | V | TA = 25°C | 5 |
| Digital Input Voltage to GND | | -0.3 | | | V | Max is VDD + 0.3 V | 5 |
| VOUT to GND | VOUT | -0.3 | | | V | Max is VDD + 0.3 V | 5 |
| Operating Temperature Range (Industrial A/B) | | -40 | | 125 | °C | | 5 |
| Storage Temperature Range | | -65 | | 160 | °C | | 5 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 5 |
| Lead Temperature, Vapor Phase | | | | 215 | °C | 60 sec | 5 |
| Lead Temperature, Infrared | | | | 220 | °C | 15 sec | 5 |
| ESD (Human Body Model) | | | | 2 | kV | | 5 |
| θJA Thermal Impedance, SC70 | θJA | | 433.34 | | °C/W | SC70 Package | 5 |
| θJC Thermal Impedance, SC70 | θJC | | 149.47 | | °C/W | SC70 Package | 5 |
| Resolution | | | 10 | | Bits | AD5611 | 3 |
| Full-Scale Error | | | 0.5 | | mV | All 1s loaded to DAC register; printed as ±0.5 | 3 |
| Zero-Code Error Drift | | | 5 | | µV/°C | | 3 |
| Gain Temperature Coefficient | | | 2 | | ppm FSR/°C | | 3 |
| Slew Rate | | | 0.5 | | V/µs | | 3 |
| Short-Circuit Current | | | 15 | | mA | VDD = 3 V/5 V | 3 |
| DC Output Impedance | | | 0.5 | | Ω | | 3 |
| Output Noise Spectral Density | | | 120 | | nV/√Hz | DAC code = midscale, 1 kHz | 3 |
| Pin Input Capacitance | | | 3 | | pF | | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | | ESD (Human Body Model) 2.0 kV Stresses at or above those listed under Absolute Maximum | 5 |
## CAD (KiCad official)
- Symbol: `AD5611BKSZ-500RL7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files: `ad5611bksz-500rl7-etched.step` / `ad5611bksz-500rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5611bksz-500rl7.step` / `ad5611bksz-500rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5601_5611_5621.pdf) (21 pp, sha256 `05bad4273b7f5318`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5611bksz-500rl7-datasheet.pdf)