component
AD5611AKSZ-REEL7
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5611AKSZ-REEL7
Analog Devices · Pre-ordered Chips · SC-70-6
AD5611AKSZ-REEL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Level-triggered active-low frame synchronization input; the DAC updates after the 16th clock unless SYNC is taken high first, in which case the rising edge acts as an interrupt and the write is ignored. |
| 2 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge, at rates up to 30 MHz. |
| 3 | SDIN | input | Serial data input to a 16-bit shift register, with data clocked in on the falling edge of the serial clock. |
| 4 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V, to be decoupled to GND. |
| 5 | GND | power_in | Ground reference point for all circuitry on the device. |
| 6 | VOUT | output | Analog DAC output voltage, driven by an output amplifier with rail-to-rail operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Interface ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD | VDD | 2.7 | 5.5 | V | All digital inputs at 0 V or VDD | 4 | |
| IDD normal mode, DAC active | IDD | 75 | 100 | µA | DAC active, excluding load current; VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 4 | |
| IDD normal mode, DAC active | IDD | 60 | 90 | µA | DAC active, excluding load current; VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND | 4 | |
| Relative accuracy (INL), A version | INL | -4 | 4 | LSB | Linearity calculated using reduced code range, AD5611 from Code 16 to Code 1008 | 3 | |
| Differential nonlinearity (DNL) | DNL | -0.5 | 0.5 | LSB | Guaranteed monotonic by design | 3 | |
| Full-scale error | -0.5 | 0.5 | mV | All 1s loaded to DAC register | 3 | ||
| Offset error | -10 | 0.063 | 10 | mV | 3 | ||
| Gain error | -0.037 | 0.0004 | 0.037 | %FSR | 3 | ||
| Zero-code error | 0.5 | 10 | mV | All 0s loaded to DAC register | 3 | ||
| Input current | -2 | 2 | µA | Total current flowing into all pins | 3 | ||
| Input high voltage VINH | VINH | 1.8 | V | VDD = 4.7 V to 5.5 V | 3 | ||
| Input high voltage VINH | VINH | 1.4 | V | VDD = 2.7 V to 3.6 V | 3 | ||
| Input low voltage VINL | VINL | 0.8 | V | VDD = 4.7 V to 5.5 V | 3 | ||
| Input low voltage VINL | VINL | 0.6 | V | VDD = 2.7 V to 3.6 V | 3 | ||
| Output voltage range | 0 | V | 3 | ||||
| Output voltage settling time | 6 | 10 | µs | Code ¼ scale to ¾ scale | 3 | ||
| Absolute maximum VDD to GND | VDD | -0.3 | 7 | V | VDD to GND | 5 | |
| Digital input voltage to GND | -0.3 | V | Printed maximum is VDD + 0.3 V | 5 | |||
| VOUT to GND | VOUT | -0.3 | V | Printed maximum is VDD + 0.3 V | 5 | ||
| Operating temperature range (A/B grades) | -40 | 125 | °C | Industrial (A/B grades) | 5 | ||
| Storage temperature range | -65 | 160 | °C | 5 | |||
| Maximum junction temperature | 150 | °C | 5 | ||||
| Thermal impedance junction-to-ambient, SC70 package | θJA | 433.34 | °C/W | SC70 package | 5 | ||
| Thermal impedance junction-to-case, SC70 package | θJC | 149.47 | °C/W | SC70 package | 5 | ||
| ESD, human body model | 2 | kV | Human body model | 5 | |||
| Lead temperature, vapor phase soldering | 215 | °C | 60 sec | 5 | |||
| Lead temperature, infrared soldering | 220 | °C | 15 sec | 5 | |||
| SCLK cycle time | t1 | 33 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| SCLK high time | t2 | 5 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| SCLK low time | t3 | 5 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| SYNC to SCLK falling edge setup time | t4 | 10 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| Data setup time | t5 | 5 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| Data hold time | t6 | 4.5 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| SCLK falling edge to SYNC rising edge | t7 | 0 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| Minimum SYNC high time | t8 | 20 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| SYNC rising edge to next SCLK falling edge ignored | t9 | 13 | ns | VDD = 2.7 V to 5.5 V | 4 | ||
| Power-down IDD | IDD | 0.5 | µA | VIH = VDD and VIL = GND; VDD = 4.5 V to 5.5 V | 4 | ||
| Power-down IDD | IDD | 0.2 | µA | VIH = VDD and VIL = GND; VDD = 2.7 V to 3.6 V | 4 | ||
| Output slew rate | 0.5 | V/µs | 3 | ||||
| Capacitive load stability | 470 | pF | RL = ∞ | 3 | |||
| Capacitive load stability | 1000 | pF | RL = 2 kΩ | 3 | |||
| Output noise spectral density | 120 | nV/√Hz | DAC code = midscale, 1 kHz | 3 | |||
| Output noise | 2 | µV rms | DAC code = midscale, 0.1 Hz to 10 Hz bandwidth | 3 | |||
| Digital-to-analog glitch impulse | 5 | nV-s | 1 LSB change around major carry | 3 | |||
| Digital feedthrough | 0.2 | nV-s | 3 | ||||
| Short-circuit current | 15 | mA | VDD = 3 V/5 V | 3 | |||
| DC output impedance | 0.5 | Ω | 3 | ||||
| Pin input capacitance | 3 | pF | 3 | ||||
| Zero-code error drift | 5 | µV/°C | 3 | ||||
| Gain temperature coefficient | 2 | ppm FSR/°C | 3 | ||||
| Power efficiency IOUT/IDD | 96 | % | ILOAD = 2 mA and VDD = ±5 V (as printed) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | ESD (Human Body Model) 2.0 kV Stresses at or above those listed under Absolute Maximum | 5 |
CAD (KiCad official)
- Symbol:
AD5611AKSZ-REEL7 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files:
ad5611aksz-reel7-etched.step/ad5611aksz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5611aksz-reel7.step/ad5611aksz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (21 pp, sha256
05bad4273b7f5318, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5611AKSZ-REEL7
**Analog Devices** · Pre-ordered Chips · SC-70-6
AD5611AKSZ-REEL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Level-triggered active-low frame synchronization input; the DAC updates after the 16th clock unless SYNC is taken high first, in which case the rising edge acts as an interrupt and the write is ignored. |
| 2 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge, at rates up to 30 MHz. |
| 3 | SDIN | input | Serial data input to a 16-bit shift register, with data clocked in on the falling edge of the serial clock. |
| 4 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V, to be decoupled to GND. |
| 5 | GND | power_in | Ground reference point for all circuitry on the device. |
| 6 | VOUT | output | Analog DAC output voltage, driven by an output amplifier with rail-to-rail operation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Interface ICs |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD | VDD | 2.7 | | 5.5 | V | All digital inputs at 0 V or VDD | 4 |
| IDD normal mode, DAC active | IDD | | 75 | 100 | µA | DAC active, excluding load current; VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 4 |
| IDD normal mode, DAC active | IDD | | 60 | 90 | µA | DAC active, excluding load current; VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND | 4 |
| Relative accuracy (INL), A version | INL | -4 | | 4 | LSB | Linearity calculated using reduced code range, AD5611 from Code 16 to Code 1008 | 3 |
| Differential nonlinearity (DNL) | DNL | -0.5 | | 0.5 | LSB | Guaranteed monotonic by design | 3 |
| Full-scale error | | -0.5 | | 0.5 | mV | All 1s loaded to DAC register | 3 |
| Offset error | | -10 | 0.063 | 10 | mV | | 3 |
| Gain error | | -0.037 | 0.0004 | 0.037 | %FSR | | 3 |
| Zero-code error | | | 0.5 | 10 | mV | All 0s loaded to DAC register | 3 |
| Input current | | -2 | | 2 | µA | Total current flowing into all pins | 3 |
| Input high voltage VINH | VINH | 1.8 | | | V | VDD = 4.7 V to 5.5 V | 3 |
| Input high voltage VINH | VINH | 1.4 | | | V | VDD = 2.7 V to 3.6 V | 3 |
| Input low voltage VINL | VINL | | | 0.8 | V | VDD = 4.7 V to 5.5 V | 3 |
| Input low voltage VINL | VINL | | | 0.6 | V | VDD = 2.7 V to 3.6 V | 3 |
| Output voltage range | | 0 | | | V | | 3 |
| Output voltage settling time | | | 6 | 10 | µs | Code ¼ scale to ¾ scale | 3 |
| Absolute maximum VDD to GND | VDD | -0.3 | | 7 | V | VDD to GND | 5 |
| Digital input voltage to GND | | -0.3 | | | V | Printed maximum is VDD + 0.3 V | 5 |
| VOUT to GND | VOUT | -0.3 | | | V | Printed maximum is VDD + 0.3 V | 5 |
| Operating temperature range (A/B grades) | | -40 | | 125 | °C | Industrial (A/B grades) | 5 |
| Storage temperature range | | -65 | | 160 | °C | | 5 |
| Maximum junction temperature | | | | 150 | °C | | 5 |
| Thermal impedance junction-to-ambient, SC70 package | θJA | | 433.34 | | °C/W | SC70 package | 5 |
| Thermal impedance junction-to-case, SC70 package | θJC | | 149.47 | | °C/W | SC70 package | 5 |
| ESD, human body model | | | | 2 | kV | Human body model | 5 |
| Lead temperature, vapor phase soldering | | | | 215 | °C | 60 sec | 5 |
| Lead temperature, infrared soldering | | | | 220 | °C | 15 sec | 5 |
| SCLK cycle time | t1 | 33 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| SCLK high time | t2 | 5 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| SCLK low time | t3 | 5 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| SYNC to SCLK falling edge setup time | t4 | 10 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| Data setup time | t5 | 5 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| Data hold time | t6 | 4.5 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| SCLK falling edge to SYNC rising edge | t7 | 0 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| Minimum SYNC high time | t8 | 20 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| SYNC rising edge to next SCLK falling edge ignored | t9 | 13 | | | ns | VDD = 2.7 V to 5.5 V | 4 |
| Power-down IDD | IDD | | 0.5 | | µA | VIH = VDD and VIL = GND; VDD = 4.5 V to 5.5 V | 4 |
| Power-down IDD | IDD | | 0.2 | | µA | VIH = VDD and VIL = GND; VDD = 2.7 V to 3.6 V | 4 |
| Output slew rate | | | 0.5 | | V/µs | | 3 |
| Capacitive load stability | | | 470 | | pF | RL = ∞ | 3 |
| Capacitive load stability | | | 1000 | | pF | RL = 2 kΩ | 3 |
| Output noise spectral density | | | 120 | | nV/√Hz | DAC code = midscale, 1 kHz | 3 |
| Output noise | | | 2 | | µV rms | DAC code = midscale, 0.1 Hz to 10 Hz bandwidth | 3 |
| Digital-to-analog glitch impulse | | | 5 | | nV-s | 1 LSB change around major carry | 3 |
| Digital feedthrough | | | 0.2 | | nV-s | | 3 |
| Short-circuit current | | | 15 | | mA | VDD = 3 V/5 V | 3 |
| DC output impedance | | | 0.5 | | Ω | | 3 |
| Pin input capacitance | | | 3 | | pF | | 3 |
| Zero-code error drift | | | 5 | | µV/°C | | 3 |
| Gain temperature coefficient | | | 2 | | ppm FSR/°C | | 3 |
| Power efficiency IOUT/IDD | | | 96 | | % | ILOAD = 2 mA and VDD = ±5 V (as printed) | 4 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | | ESD (Human Body Model) 2.0 kV Stresses at or above those listed under Absolute Maximum | 5 |
## CAD (KiCad official)
- Symbol: `AD5611AKSZ-REEL7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files: `ad5611aksz-reel7-etched.step` / `ad5611aksz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5611aksz-reel7.step` / `ad5611aksz-reel7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5601_5611_5621.pdf) (21 pp, sha256 `05bad4273b7f5318`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5611aksz-reel7-datasheet.pdf)