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AD5592RBCPZ-RL7

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Analog Devices ADC/DAC - Specialized, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5592rbcpz-rl7factory-2.0.0extractor-text

Verified AD5592RBCPZ-RL7

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5592RBCPZ-RL7 · LFCSP-16(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 54-page datasheet
  • ✓distributor: lcsc C649857, digikey 505-AD5592RBCPZ-RL7TR-ND, mouser 584-AD5592RBCPZ-RL7
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-74kuhdo5/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5592rbcpz-rl7.kicad_sym✓ ad5592rbcpz-rl7.kicad_mod✓ ad5592rbcpz-rl7.step
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Ray Publish 0.1.0 98cef32 3d ago

AD5592RBCPZ-RL7

Analog Devices · ADC/DAC - Specialized · LFCSP-16(3x3)

AD5592RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input; the AD5592R operates from 2.7 V to 5.5 V and this pin must be decoupled with a 0.1 µF capacitor to GND.
2 I/O0 bidirectional Input/output pin that can be independently configured as a DAC output, ADC input, or general-purpose digital input or output, with the function set by the I/Ox pin configuration registers.
3 I/O1 bidirectional Input/output pin that can be independently configured as a DAC output, ADC input, or general-purpose digital input or output, with the function set by the I/Ox pin configuration registers.
4 I/O2 bidirectional Input/output pin that can be independently configured as a DAC output, ADC input, or general-purpose digital input or output, with the function set by the I/Ox pin configuration registers.
5 I/O3 bidirectional Input/output pin that can be independently configured as a DAC output, ADC input, or general-purpose digital input or output, with the function set by the I/Ox pin configuration registers.
6 VREF power_in Reference input/output: provides the 2.5 V internal reference when enabled (0.1 µF to GND recommended); when the internal reference is disabled an external reference of 1 V to VDD must be applied.
7 SDO output Serial data output carrying ADC conversion results, register reads and temperature sensor data; bits are clocked out on the rising edge of SCLK and the MSB appears on the falling edge of SYNC.
8 I/O4 bidirectional Input/output pin that can be independently configured as a DAC output, ADC input, or general-purpose digital input or output, with the function set by the I/Ox pin configuration registers.
9 I/O5 bidirectional Input/output pin that can be independently configured as a DAC output, ADC input, or general-purpose digital input or output, with the function set by the I/Ox pin configuration registers.
10 I/O6 bidirectional Input/output pin that can be independently configured as a DAC output, ADC input, or general-purpose digital input or output, with the function set by the I/Ox pin configuration registers.
11 I/O7 bidirectional Input/output pin that can be configured as a DAC, ADC, or general-purpose digital input or output, or as a BUSY output indicating when an ADC conversion is taking place.
12 GND power_in Ground reference point for all circuitry on the AD5592R.
13 SDI input Serial data input; data for the DACs and control registers is clocked into the register on the falling edge of SCLK.
14 SCLK input Serial clock input; data can be clocked at up to 50 MHz when writing to the DACs and has a maximum speed of 20 MHz for conversions or reads from the AD5592R.
15 RESET input Asynchronous active-low reset; tie this pin high for normal operation, and a low level resets the device to its default configuration.
16 SYNC input Active-low frame synchronization input; when SYNC goes low, data is transferred in on the falling edges of the next 16 clocks.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-16(3x3)
Category ADC/DAC/Data Conversion
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Specified Performance temperature range -40 105 °C 6
Operating Temperature Range (TA to TJ) -40 125 °C TA to TJ 12
Temperature sensor accuracy -3 3 °C 5 sample averaging 8
Power supply voltage VDD 2.7 5.5 V 8
VREF input voltage (external reference) VREF 1 V 7
DC leakage current, REFERENCE INPUT -1 1 µA No I/Ox pins configured as DACs 7
VREF output voltage VREF 2.495 2.5 2.505 V TA = 25°C 7
Output current load capability -5 5 mA VDD ≥ 3 V 8
GPIO input current -1 1 µA 8
Logic input current IIN -1 1 µA Typically 10 nA, RESET = 1 µA typical 8
ADC input range (0 to VREF) 0 V 6
ADC input range (0 to 2 × VREF) 0 V 6
ADC integral nonlinearity (INL) -2 2 LSB 6
ADC differential nonlinearity (DNL) -1 1 LSB 6
ADC offset error -5 5 mV 6
DAC integral nonlinearity (INL) -1 1 LSB 6
DAC differential nonlinearity (DNL) -1 1 LSB 6
DAC offset error -3 3 mV 6
DAC gain error -0.2 0.2 % FSR Output range = 0 V to VREF 7
DAC gain error -0.1 0.1 % FSR Output range = 0 V to 2 × VREF 7
DC crosstalk -4 4 µV Due to single channel, full-scale output change 7
SCLK cycle time, write operation t1 33 ns 2.7 V ≤ VDD < 3 V 9
SCLK cycle time, write operation t1 20 ns 3 V ≤ VDD ≤ 5.5 V 9
SCLK cycle time, read operation t1 50 ns 2.7 V ≤ VDD < 3 V 9
SCLK high time t2 16 ns 2.7 V ≤ VDD < 3 V 9
SCLK high time t2 10 ns 3 V ≤ VDD ≤ 5.5 V 9
SCLK low time t3 16 ns 2.7 V ≤ VDD < 3 V 9
SCLK low time t3 10 ns 3 V ≤ VDD ≤ 5.5 V 9
SYNC falling edge to SCLK falling edge setup time t4 15 ns 2.7 V ≤ VDD < 3 V 10
SYNC falling edge to SCLK falling edge setup time t4 10 ns 3 V ≤ VDD ≤ 5.5 V 10
SYNC falling edge to SCLK falling edge setup time (ADC read) t4 1.65 µs 2.7 V ≤ VDD < 3 V; when reading an ADC conversion 10
Data setup time t5 7 ns 2.7 V ≤ VDD < 3 V 10
Data hold time t6 5 ns 2.7 V ≤ VDD < 3 V 10
SCLK falling edge to SYNC rising edge t7 15 ns 2.7 V ≤ VDD < 3 V 10
SCLK falling edge to SYNC rising edge t7 10 ns 3 V ≤ VDD ≤ 5.5 V 10
Minimum SYNC high time, register write t8 30 ns 2.7 V ≤ VDD < 3 V 10
Minimum SYNC high time, register read t8 60 ns 2.7 V ≤ VDD < 3 V 10
SCLK rising edge to SDO valid t10 25 ns 2.7 V ≤ VDD < 3 V 10
RESET low pulse width t11 250 ns 2.7 V ≤ VDD < 3 V; not shown in Figure 4 10
VDD to GND VDD -0.3 7 V 12
Analog input voltage to GND -0.3 V 12
Digital input voltage to GND (AD5592R) -0.3 V 12
Digital output voltage to GND (AD5592R) -0.3 V 12
VREF to GND VREF -0.3 V 12
Storage temperature range -65 150 °C 12
Junction temperature (TJ max) TJ max 150 °C 12
Thermal resistance, junction to ambient θJA 92.4 °C/W LFCSP CP-16-32; JEDEC 2S2P board 12
Thermal resistance, junction to board θJB 39.6 °C/W LFCSP CP-16-32; JEDEC 2S2P board 12
Thermal resistance, junction to case top θJC-TOP 48.2 °C/W LFCSP CP-16-32; JEDEC 1S board 12
Junction to package top characterization parameter ΨJT 0.9 °C/W LFCSP CP-16-32; JEDEC natural convection 12
Junction to board characterization parameter ΨJB 37.4 °C/W LFCSP CP-16-32; JEDEC natural convection 12

CAD (KiCad official)

  • Symbol: AD5592RBCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: ad5592rbcpz-rl7-etched.step / ad5592rbcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5592rbcpz-rl7.step / ad5592rbcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (54 pp, sha256 f64878eb9d2c5f02, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF