component
AD5570ARSZ
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), SSOP-16-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAD5570ARSZ
Analog Devices · Digital To Analog Converters (DACs) · SSOP-16-208mil
AD5570ARSZ from Analog Devices, in a SSOP-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS | power_in | Negative Analog Supply Voltage: −12 V ± 5% to −15 V ± 10% for specified performance. |
| 2 | VDD | power_in | Positive Analog Supply Voltage: 12 V ± 5% to 15 V ± 10% for specified performance. |
| 3 | CLR | input | Level-sensitive, active-low input; a falling edge of CLR resets VOUT to AGND while the register contents are untouched. |
| 4 | LDAC | input | Active-low control input that transfers the input register contents to the DAC register, and can be tied permanently low so outputs update on the rising edge of SYNC. |
| 5 | SYNC | input | Active-low frame synchronization input; when it goes low it powers on the SCLK and SDIN buffers and enables the input shift register, with data clocked in on the falling edges of the following 16 clocks. |
| 6 | SCLK | input | Serial clock input; data is clocked into the input register on its falling edge, at transfer rates of up to 8 MHz. |
| 7 | SDIN | input | Serial data input; data is clocked into the 16-bit register on the falling edge of the serial clock. |
| 8 | SDO | output | Open-drain serial data output for daisy-chaining or shift-register readback; it must be pulled to logic high with an external pull-up resistor of ~5 kΩ. |
| 9 | DGND | power_in | Digital ground, the reference for all digital circuitry. |
| 10 | PD | input | Active-low control input that puts the DAC into a power-down state. |
| 11 | AGND | power_in | Analog ground, the reference for all analog circuitry. |
| 12 | AGNDS | power_in | Analog ground sense; normally tied to AGND. |
| 13 | VOUT | output | Analog output voltage of the DAC, buffered and specified up to ±14 V output range. |
| 14 | REFGND | power_in | Reference ground; tie this pin to 0 V. |
| 15 | REFIN | input | Voltage reference input, internally buffered before being applied to the DAC; for the bipolar ±10 V output range REFIN is 5 V. |
| 16 | REFGND | power_in | Reference ground; tie this pin to 0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SSOP-16-208mil |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL) | INL | -2 | 0.6 | 2 | LSB | A/W Grade | 3 |
| Differential Nonlinearity (DNL) | DNL | -1 | 0.3 | 1 | LSB | 3 | |
| Negative Full-Scale Error | -7.5 | 0.9 | 7.5 | mV | 3 | ||
| Full-Scale Error | -6 | 1.8 | 6 | mV | 3 | ||
| Bipolar Zero Error | -7.5 | 0.9 | 7.5 | mV | 3 | ||
| Gain Error | -7.5 | 1.8 | 7.5 | mV | 3 | ||
| Gain Temperature Coefficient | -1.5 | 0.25 | 1.5 | ppm FSR/°C | 3 | ||
| Reference Input Range | 4 | 5 | 5 | V | With ±11.4 V supplies | 3 | |
| Reference Input Range | 4 | 5 | 7 | V | With ±16.5 V supplies | 3 | |
| Input Current (REFIN) | -0.1 | 0.1 | μA | 3 | |||
| Positive INL Drift Over Time | 2.5 | ppm | A/B Grades | 3 | |||
| Output Voltage Settling Time | 12 | 16 | μs | At 16 bits to ±0.5 LSB | 3 | ||
| Output Voltage Settling Time | 10 | 13 | μs | To 0.0003% | 3 | ||
| Output Voltage Settling Time | 6 | 7 | μs | 512 LSB code change | 3 | ||
| Slew Rate | 6.5 | V/μs | Measured from 10% to 90% | 3 | |||
| Digital-to-Analog Glitch Impulse | 15 | nV-s | ±12 V supplies; 1 LSB change around the major carry | 3 | |||
| Bandwidth | 20 | kHz | 3 | ||||
| Short Circuit Current | 25 | mA | 3 | ||||
| Output Noise Voltage Density | 85 | nV/Hz | f = 1 kHz; midscale loaded | 3 | |||
| DAC Output Impedance | 0.35 | 0.5 | Ω | 3 | |||
| Digital Feedthrough | 0.5 | nV-s | 3 | ||||
| Warmup Time | 5 | 12 | sec | 3 | |||
| Input Currents (logic inputs) | -0.1 | 0.1 | μA | 3 | |||
| Input High Voltage | VINH | 2 | V | 3 | |||
| Input Low Voltage | VINL | 0.8 | V | 3 | |||
| Input Capacitance | CIN | 3 | pF | 3 | |||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 1 mA | 3 | ||
| Floating-State Output Capacitance | 8 | pF | 3 | ||||
| Supply Voltage VDD/VSS | VDD/VSS | 11.4 | 16.5 | V | 4 | ||
| Positive Supply Current | IDD | 4 | 5 | mA | VOUT unloaded | 4 | |
| Negative Supply Current | ISS | 3.5 | 5 | mA | VOUT unloaded | 4 | |
| Power-Down Current | 16 | μA | VOUT unloaded | 4 | |||
| Power-Supply Sensitivity | 0.1 | LSB/V | ±15 supplies ±10%; full-scale loaded | 4 | |||
| Power Dissipation | 100 | mW | VOUT unloaded | 4 | |||
| VDD to AGND, AGNDS, DGND | VDD | -0.3 | 17 | V | 8 | ||
| VSS to AGND, AGNDS, DGND | VSS | -17 | 0.3 | V | 8 | ||
| AGND, AGNDS to DGND | -0.3 | 0.3 | V | 8 | |||
| REFGND to AGND | -0.3 | 0.3 | V | 8 | |||
| REFIN to AGND, AGNDS | -0.3 | 17 | V | 8 | |||
| REFIN to REFGND | -0.3 | 17 | V | 8 | |||
| SDO to DGND | -0.3 | 6.5 | V | 8 | |||
| Operating Temperature Range | -40 | 85 | °C | A/B Grades | 8 | ||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Maximum Junction Temperature (TJ max) | TJ | 150 | °C | 8 | |||
| ESD HBM Classification | 5 | kV | HBM classification | 8 | |||
| Thermal Impedance (16-Lead SSOP) | θJA | 139 | °C/W | 8 | |||
| Minimum SCLK cycle time | t1 | 100 | ns | Standalone | 5 | ||
| SCLK maximum frequency | fMAX | 10 | MHz | Standalone | 5 | ||
| SCLK high time | t2 | 35 | ns | Standalone | 5 | ||
| SCLK low time | t3 | 35 | ns | Standalone | 5 | ||
| SYNC to SCLK falling edge setup time | t4 | 10 | ns | Standalone | 5 | ||
| Data setup time | t5 | 35 | ns | Standalone | 5 | ||
| Data hold time | t6 | 0 | ns | Standalone | 5 | ||
| SCLK falling edge to SYNC rising edge | t7 | 45 | ns | Standalone | 5 | ||
| Minimum SYNC high time | t8 | 45 | ns | Standalone | 5 | ||
| SYNC rising edge to LDAC falling edge | t9 | 0 | ns | Standalone | 5 | ||
| LDAC pulse width | t10 | 50 | ns | Standalone | 5 | ||
| LDAC falling edge to SYNC falling edge (no update) | t11 | 0 | ns | Standalone | 5 | ||
| LDAC rising edge to SYNC rising edge (no update) | t12 | 0 | ns | Standalone | 5 | ||
| CLR pulse width | t13 | 20 | ns | Standalone | 5 |
CAD (KiCad official)
- Symbol:
AD5570ARSZ - Footprint:
Package_SO:SSOP-16_5.3x6.2mm_P0.65mm - 3D model: SSOP-16-208mil (KiCad packages3D, STEP)
- 3D model files:
ad5570arsz-etched.step/ad5570arsz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5570arsz.step/ad5570arsz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
e770e639b9cb2580, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).