component
AD5555CRUZ
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5555CRUZ
Analog Devices · Pre-ordered Chips · TSSOP-16
AD5555CRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFBA | passive | Establishes the voltage output for DAC A when this pin is connected to an external amplifier output. |
| 2 | VREFA | input | DAC A reference voltage input that establishes the DAC A full-scale output voltage; it can be tied to the VDD pin. |
| 3 | IOUTA | output | DAC A current output. |
| 4 | AGNDA | power_in | DAC A analog ground. |
| 5 | AGNDB | power_in | DAC B analog ground. |
| 6 | IOUTB | output | DAC B current output. |
| 7 | VREFB | input | DAC B reference voltage input that establishes the DAC B full-scale output voltage; it can be tied to the VDD pin. |
| 8 | RFBB | passive | Establishes the voltage output for DAC B when this pin is connected to an external amplifier output. |
| 9 | SDI | input | Serial data input; input data loads directly into the shift register. |
| 10 | RS | input | Active-low reset input that sets the input and DAC registers to all 0s or midscale, per the MSB pin (0x0000 when MSB = 0; 0x8000 for AD5545 or 0x2000 for AD5555 when MSB = 1). |
| 11 | CS | input | Active-low chip select that disables shift register loading when high and transfers serial register data to the input register when CS/LDAC returns high. |
| 12 | DGND | power_in | Digital ground pin. |
| 13 | VDD | power_in | Positive power supply input with a specified operating range of 5 V ±10% (4.5 V to 5.5 V). |
| 14 | MSB | input | Sets the output to zero scale when MSB = 0 or midscale when MSB = 1 during a RESET pulse or at power-on; can also be tied permanently to GND or VDD. |
| 15 | LDAC | input | Level-sensitive, active-low asynchronous input that transfers all input register data to the DAC registers. |
| 16 | CLK | input | Clock input; the positive edge clocks data into the shift register. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (AD5555C) | INL | -1 | 1 | LSB | 3 | ||
| Differential Nonlinearity | DNL | -1 | 1 | LSB | Monotonic | 3 | |
| Output Leakage Current | IOUT | 10 | nA | Data = 0x0000, TA = 25°C | 3 | ||
| Output Leakage Current | IOUT | 20 | nA | Data = 0x0000, TA = TA Max | 3 | ||
| Full-Scale Gain Error | GFSE | -4 | 1 | 4 | mV | Data = full scale | 3 |
| Full-Scale Temperature Coefficient | TCVFS | 1 | ppm/°C | 3 | |||
| VREF Range | VREF | -12 | 12 | V | 3 | ||
| Input Resistance | RREF | 5 | kΩ | 3 | |||
| Input Capacitance | CREF | 5 | pF | 3 | |||
| Output Current | IOUT | 2 | mA | Data = full scale | 3 | ||
| Output Capacitance | COUT | 200 | pF | Code dependent | 3 | ||
| Logic Input Low Voltage | VIL | 0.8 | V | 3 | |||
| Logic Input High Voltage | VIH | 2.4 | V | 3 | |||
| Input Leakage Current | IIL | 10 | µA | 3 | |||
| Input Capacitance | CIL | 10 | pF | 3 | |||
| Clock Input Frequency | fCLK | 50 | MHz | 3 | |||
| Clock Width High | tCH | 10 | ns | 3 | |||
| Clock Width Low | tCL | 10 | ns | 3 | |||
| CS to Clock Setup | tCSS | 0 | ns | 3 | |||
| Clock to CS Hold | tCSH | 10 | ns | 3 | |||
| Data Setup | tDS | 5 | ns | 3 | |||
| Data Hold | tDH | 10 | ns | 3 | |||
| LDAC Setup | tLDS | 5 | ns | 3 | |||
| LDAC Hold | tLDH | 10 | ns | 3 | |||
| LDAC Width | tLDAC | 10 | ns | 3 | |||
| Power Supply Range | VDD range | 4.5 | 5.5 | V | 3 | ||
| Positive Supply Current | IDD | 10 | µA | Logic inputs = 0 V | 3 | ||
| Power Dissipation | PDISS | 0.055 | mW | Logic inputs = 0 V | 3 | ||
| Power Supply Sensitivity | PSS | 0.006 | %/% | ∆VDD = ±5% | 3 | ||
| Output Voltage Setting Time | tS | 0.5 | µs | To ±0.1% full scale, data = zero scale to full scale to zero scale | 4 | ||
| Reference Multiplying Bandwidth | BW | 6.9 | MHz | VREF = 100 mV rms, data = full scale, C1 = 5.6 pF | 4 | ||
| DAC Glitch Impulse | Q | -2 | nV-s | VREF = 0 V, data = midscale minus 1 to midscale | 4 | ||
| Feedthrough Error | VOUT/VREF | -81 | dB | Data = zero scale, VREF = 100 mV rms, f = 1 kHz, same channel | 4 | ||
| Digital Feedthrough | Q | 7 | nV-s | CS = logic high and fCLK = 1 MHz | 4 | ||
| Total Harmonic Distortion | THD | -104 | dB | VREF = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz | 4 | ||
| Analog Crosstalk | CTA | -95 | dB | VREFB = 0 V, measure VOUTB with VREFA = 5 V p-p sine wave, data = full scale, f = 1 kHz to 10 kHz | 4 | ||
| Output Spot Noise Voltage | eN | 12 | nV/√Hz | f = 1 kHz, BW = 1 Hz | 4 | ||
| VDD to GND | -0.3 | 8 | V | 5 | |||
| VREF to GND | -18 | 18 | V | 5 | |||
| Logic Inputs to GND | -0.3 | 8 | V | 5 | |||
| Input Current to Any Pin except Supplies | -50 | 50 | mA | 5 | |||
| Thermal Resistance | θJA | 150 | °C/W | 16-Lead TSSOP | 5 | ||
| Maximum Junction Temperature | TJ max | 150 | °C | 5 | |||
| Operating Temperature Range | -40 | 85 | °C | 5 | |||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Lead Temperature (RU-16) | 215 | °C | Vapor Phase, 60 sec | 5 | |||
| Lead Temperature (RU-16) | 220 | °C | Infrared, 15 sec | 5 |
CAD (KiCad official)
- Symbol:
AD5555CRUZ - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad5555cruz-etched.step/ad5555cruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5555cruz.step/ad5555cruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (23 pp, sha256
641a20e525b8da4d, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5555CRUZ
**Analog Devices** · Pre-ordered Chips · TSSOP-16
AD5555CRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFBA | passive | Establishes the voltage output for DAC A when this pin is connected to an external amplifier output. |
| 2 | VREFA | input | DAC A reference voltage input that establishes the DAC A full-scale output voltage; it can be tied to the VDD pin. |
| 3 | IOUTA | output | DAC A current output. |
| 4 | AGNDA | power_in | DAC A analog ground. |
| 5 | AGNDB | power_in | DAC B analog ground. |
| 6 | IOUTB | output | DAC B current output. |
| 7 | VREFB | input | DAC B reference voltage input that establishes the DAC B full-scale output voltage; it can be tied to the VDD pin. |
| 8 | RFBB | passive | Establishes the voltage output for DAC B when this pin is connected to an external amplifier output. |
| 9 | SDI | input | Serial data input; input data loads directly into the shift register. |
| 10 | RS | input | Active-low reset input that sets the input and DAC registers to all 0s or midscale, per the MSB pin (0x0000 when MSB = 0; 0x8000 for AD5545 or 0x2000 for AD5555 when MSB = 1). |
| 11 | CS | input | Active-low chip select that disables shift register loading when high and transfers serial register data to the input register when CS/LDAC returns high. |
| 12 | DGND | power_in | Digital ground pin. |
| 13 | VDD | power_in | Positive power supply input with a specified operating range of 5 V ±10% (4.5 V to 5.5 V). |
| 14 | MSB | input | Sets the output to zero scale when MSB = 0 or midscale when MSB = 1 during a RESET pulse or at power-on; can also be tied permanently to GND or VDD. |
| 15 | LDAC | input | Level-sensitive, active-low asynchronous input that transfers all input register data to the DAC registers. |
| 16 | CLK | input | Clock input; the positive edge clocks data into the shift register. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Interface ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (AD5555C) | INL | -1 | | 1 | LSB | | 3 |
| Differential Nonlinearity | DNL | -1 | | 1 | LSB | Monotonic | 3 |
| Output Leakage Current | IOUT | | | 10 | nA | Data = 0x0000, TA = 25°C | 3 |
| Output Leakage Current | IOUT | | | 20 | nA | Data = 0x0000, TA = TA Max | 3 |
| Full-Scale Gain Error | GFSE | -4 | 1 | 4 | mV | Data = full scale | 3 |
| Full-Scale Temperature Coefficient | TCVFS | | | 1 | ppm/°C | | 3 |
| VREF Range | VREF | -12 | | 12 | V | | 3 |
| Input Resistance | RREF | | | 5 | kΩ | | 3 |
| Input Capacitance | CREF | | | 5 | pF | | 3 |
| Output Current | IOUT | | | 2 | mA | Data = full scale | 3 |
| Output Capacitance | COUT | | | 200 | pF | Code dependent | 3 |
| Logic Input Low Voltage | VIL | | | 0.8 | V | | 3 |
| Logic Input High Voltage | VIH | 2.4 | | | V | | 3 |
| Input Leakage Current | IIL | | | 10 | µA | | 3 |
| Input Capacitance | CIL | | | 10 | pF | | 3 |
| Clock Input Frequency | fCLK | | | 50 | MHz | | 3 |
| Clock Width High | tCH | 10 | | | ns | | 3 |
| Clock Width Low | tCL | 10 | | | ns | | 3 |
| CS to Clock Setup | tCSS | 0 | | | ns | | 3 |
| Clock to CS Hold | tCSH | 10 | | | ns | | 3 |
| Data Setup | tDS | 5 | | | ns | | 3 |
| Data Hold | tDH | 10 | | | ns | | 3 |
| LDAC Setup | tLDS | 5 | | | ns | | 3 |
| LDAC Hold | tLDH | 10 | | | ns | | 3 |
| LDAC Width | tLDAC | 10 | | | ns | | 3 |
| Power Supply Range | VDD range | 4.5 | | 5.5 | V | | 3 |
| Positive Supply Current | IDD | | | 10 | µA | Logic inputs = 0 V | 3 |
| Power Dissipation | PDISS | | | 0.055 | mW | Logic inputs = 0 V | 3 |
| Power Supply Sensitivity | PSS | | | 0.006 | %/% | ∆VDD = ±5% | 3 |
| Output Voltage Setting Time | tS | | | 0.5 | µs | To ±0.1% full scale, data = zero scale to full scale to zero scale | 4 |
| Reference Multiplying Bandwidth | BW | | | 6.9 | MHz | VREF = 100 mV rms, data = full scale, C1 = 5.6 pF | 4 |
| DAC Glitch Impulse | Q | | | -2 | nV-s | VREF = 0 V, data = midscale minus 1 to midscale | 4 |
| Feedthrough Error | VOUT/VREF | | | -81 | dB | Data = zero scale, VREF = 100 mV rms, f = 1 kHz, same channel | 4 |
| Digital Feedthrough | Q | | | 7 | nV-s | CS = logic high and fCLK = 1 MHz | 4 |
| Total Harmonic Distortion | THD | | | -104 | dB | VREF = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz | 4 |
| Analog Crosstalk | CTA | | | -95 | dB | VREFB = 0 V, measure VOUTB with VREFA = 5 V p-p sine wave, data = full scale, f = 1 kHz to 10 kHz | 4 |
| Output Spot Noise Voltage | eN | | | 12 | nV/√Hz | f = 1 kHz, BW = 1 Hz | 4 |
| VDD to GND | | -0.3 | | 8 | V | | 5 |
| VREF to GND | | -18 | | 18 | V | | 5 |
| Logic Inputs to GND | | -0.3 | | 8 | V | | 5 |
| Input Current to Any Pin except Supplies | | -50 | | 50 | mA | | 5 |
| Thermal Resistance | θJA | | | 150 | °C/W | 16-Lead TSSOP | 5 |
| Maximum Junction Temperature | TJ max | | | 150 | °C | | 5 |
| Operating Temperature Range | | -40 | | 85 | °C | | 5 |
| Storage Temperature Range | | -65 | | 150 | °C | | 5 |
| Lead Temperature (RU-16) | | | | 215 | °C | Vapor Phase, 60 sec | 5 |
| Lead Temperature (RU-16) | | | | 220 | °C | Infrared, 15 sec | 5 |
## CAD (KiCad official)
- Symbol: `AD5555CRUZ`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ad5555cruz-etched.step` / `ad5555cruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5555cruz.step` / `ad5555cruz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5545_5555.pdf) (23 pp, sha256 `641a20e525b8da4d`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5555cruz-datasheet.pdf)