AD5551BRZ-REEL7

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  "slug": "ad5551brz-reel7",
  "title": "AD5551BRZ-REEL7",
  "brief": "Analog Devices Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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    "interface ics",
    "ad5551brz-reel7",
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  "component": {
    "mpn": "AD5551BRZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Interface ICs",
    "subcategory": "Pre-ordered Chips",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5551_5552.pdf",
    "parts": {
      "symbol": "ad5551brz-reel7.kicad_sym",
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      "lbr": "ad5551brz-reel7.lbr"
    },
    "distributor_links": {
      "lcsc": "C578224",
      "digikey": "AD5551BRZ-REEL7TR-ND",
      "mouser": "584-AD5551BRZ-R7"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T19:58:21Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AD5551BRZ-REEL7TR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD5551BRZ-R7",
        "status": "found",
        "lifecycle": "Restricted Availability"
      }
    },
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      {
        "number": "1",
        "name": "VOUT",
        "type": "output",
        "description": "Analog output voltage from the DAC, which swings from 0 V to VREF − 1 LSB in unipolar operation and is unbuffered, so it is rated to drive loads of 60 kΩ directly."
      },
      {
        "number": "2",
        "name": "AGND",
        "type": "power_in",
        "description": "Ground reference point for the analog circuitry, which must stay within −0.3 V to +0.3 V of DGND per the absolute maximum ratings."
      },
      {
        "number": "3",
        "name": "VREF",
        "type": "power_in",
        "description": "Voltage reference input for the DAC, which should be driven from 2 V to VDD (reference input range 2.0 V to VDD) from a low-impedance source."
      },
      {
        "number": "4",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select that frames the serial data input, so data can only be loaded while CS is low and the DAC updates on its rising edge."
      },
      {
        "number": "5",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input whose data is latched on the rising edge, with a duty cycle between 40% and 60% and a maximum SCLK frequency of 25 MHz."
      },
      {
        "number": "6",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input that accepts 14-bit words clocked in MSB first on the rising edge of SCLK, with digital input voltage limited to DGND −0.3 V to VDD + 0.3 V."
      },
      {
        "number": "7",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground reference for the digital circuitry."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
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      }
    ],
    "provenance": {
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        "guard_notes": [
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        "pages_sent": 16,
        "cost_usd": 0.0823,
        "at": "2026-10-30T19:58:07"
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        "pages": 16,
        "sha256": "0381a591725044ad",
        "source_tier": "mfr"
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