# AD5545BRUZ

**Analog Devices** · Digital To Analog Converters (DACs) · TSSOP-16

AD5545BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFBA | passive | Establishes the DAC A voltage output when this pin is connected to an external amplifier output. |
| 2 | VREFA | input | DAC A reference voltage input that establishes the DAC A full-scale output voltage, with a VREF range of −12 V to +12 V, and it can be tied to VDD. |
| 3 | IOUTA | output | DAC A current output. |
| 4 | AGNDA | power_in | DAC A analog ground. |
| 5 | AGNDB | power_in | DAC B analog ground. |
| 6 | IOUTB | output | DAC B current output. |
| 7 | VREFB | input | DAC B reference voltage input that establishes the DAC B full-scale output voltage, with a VREF range of −12 V to +12 V, and it can be tied to VDD. |
| 8 | RFBB | passive | Establishes the DAC B voltage output when this pin is connected to an external amplifier output. |
| 9 | SDI | input | Serial data input that loads data directly into the shift register. |
| 10 | RS | input | Active-low reset input that sets the input and DAC registers to all 0s or midscale, giving 0x0000 when MSB = 0 and 0x8000 (AD5545) or 0x2000 (AD5555) when MSB = 1. |
| 11 | CS | input | Active-low chip select that disables shift register loading when high and transfers serial register data to the input register when CS/LDAC returns high. |
| 12 | DGND | power_in | Digital ground pin. |
| 13 | VDD | power_in | Positive power supply input with a specified operating range of 5 V ± 10% (4.5 V to 5.5 V). |
| 14 | MSB | input | Sets the output to zero scale when MSB = 0 or midscale when MSB = 1 during a RESET pulse or at power-on, and can also be tied permanently to GND or VDD. |
| 15 | LDAC | input | Level-sensitive active-low strobe that asynchronously transfers input register data to the DAC registers. |
| 16 | CLK | input | Clock input whose positive edge clocks data into the shift register, with a clock input frequency of up to 50 MHz. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy INL (AD5545B grade) | INL | -2 |  | 2 | LSB |  | 3 |
| Differential Nonlinearity | DNL | -1 |  | 1 | LSB | Monotonic | 3 |
| Output Leakage Current | IOUT |  |  | 10 | nA | Data = 0x0000, TA = 25°C | 3 |
| Output Leakage Current | IOUT |  |  | 20 | nA | Data = 0x0000, TA = TA Max | 3 |
| Full-Scale Gain Error | GFSE | -4 |  | 4 | mV | Data = full scale | 3 |
| Full-Scale Temperature Coefficient | TCVFS |  |  | 1 | ppm/°C |  | 3 |
| VREF Range | VREF | -12 |  | 12 | V |  | 3 |
| Logic Input Low Voltage | VIL |  |  | 0.8 | V |  | 3 |
| Logic Input High Voltage | VIH | 2.4 |  |  | V |  | 3 |
| Input Leakage Current | IIL |  |  | 10 | µA |  | 3 |
| Power Supply Range | VDD | 4.5 |  | 5.5 | V | VDD range | 3 |
| Positive Supply Current | IDD |  |  | 10 | µA | Logic inputs = 0 V | 3 |
| Power Dissipation | PDISS |  |  | 0.055 | mW | Logic inputs = 0 V | 3 |
| Power Supply Sensitivity | PSS |  |  | 0.006 | %/% | ΔVDD = ±5% | 3 |
| Clock Input Frequency | fCLK |  |  | 50 | MHz |  | 3 |
| Clock Width High | tCH | 10 |  |  | ns |  | 3 |
| Clock Width Low | tCL | 10 |  |  | ns |  | 3 |
| CS to Clock Setup | tCSS | 0 |  |  | ns |  | 3 |
| Clock to CS Hold | tCSH | 10 |  |  | ns |  | 3 |
| Data Setup | tDS | 5 |  |  | ns |  | 3 |
| Data Hold | tDH | 10 |  |  | ns |  | 3 |
| LDAC Setup | tLDS | 5 |  |  | ns |  | 3 |
| LDAC Hold | tLDH | 10 |  |  | ns |  | 3 |
| LDAC Width | tLDAC | 10 |  |  | ns |  | 3 |
| Output Voltage Setting Time | tS |  |  | 0.5 | µs | To ±0.1% full scale, data = zero scale to full scale to zero scale | 4 |
| VDD to GND | VDD | -0.3 |  | 8 | V |  | 5 |
| VREF to GND | VREF | -18 |  | 18 | V |  | 5 |
| Logic Inputs to GND |  | -0.3 |  | 8 | V |  | 5 |
| V(IOUT) to GND | V(IOUT) | -0.3 |  |  | V | Upper limit printed as VDD + 0.3 V | 5 |
| Input Current to Any Pin except Supplies |  | -50 |  | 50 | mA |  | 5 |
| Thermal Resistance θJA (16-Lead TSSOP) | θJA |  | 150 |  | °C/W | 16-lead TSSOP | 5 |
| Maximum Junction Temperature | TJ max |  |  | 150 | °C |  | 5 |
| Operating Temperature Range |  | -40 |  | 85 | °C |  | 5 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 5 |
| Lead Temperature (Vapor Phase) |  |  |  | 215 | °C | RU-16 vapor phase, 60 sec | 5 |
| Lead Temperature (Infrared) |  |  |  | 220 | °C | RU-16 infrared, 15 sec | 5 |

## CAD (KiCad official)

- Symbol: `AD5545BRUZ`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ad5545bruz-etched.step` / `ad5545bruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5545bruz.step` / `ad5545bruz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5545_5555.pdf) (23 pp, sha256 `641a20e525b8da4d`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5545bruz-datasheet.pdf)