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AD5543BRMZ
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Analog Devices Digital To Analog Converters (DACs), MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5543BRMZ
Analog Devices · Digital To Analog Converters (DACs) · MSOP-8
AD5543BRMZ from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLK | input | Clock input that is positive-edge triggered and clocks data into the shift register, with a 50 MHz maximum clock input frequency and 10 ns minimum clock high and low widths. |
| 2 | SDI | input | Serial register input where data loads directly into the shift register MSB first, and extra leading bits are ignored. |
| 3 | RFB | passive | Internal matching feedback resistor (5 kΩ nominal) that connects to the external operational amplifier output for voltage output, and VDD must be powered for continuity when measuring it. |
| 4 | VREF | power_in | DAC reference input that establishes the full-scale voltage over a range of −15 V to +15 V (min/max) with constant input resistance versus code. |
| 5 | IOUT | output | DAC current output that connects to the inverting terminal of the external precision I-to-V operational amplifier, typically 2 mA full-scale for data 0xFFFF on the AD5543. |
| 6 | GND | power_in | Analog and digital ground reference for the device. |
| 7 | VDD | power_in | Positive power supply input specified for 5 V ±10% operation (4.5 V min to 5.5 V max), which also powers the internal logic that drives the DAC switches. |
| 8 | CS | input | Active-low chip select that transfers shift register data to the DAC register on its rising edge, and CLK must not toggle during this strobe. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), Grade AD5543B | INL | -2 | 2 | LSB | Grade: AD5543B | 3 | |
| Differential Nonlinearity | DNL | -1 | 1 | LSB | Monotonic | 3 | |
| Output Leakage Current | IOUT | 10 | nA | Data = 0x0000, TA = 25°C | 3 | ||
| Output Leakage Current | IOUT | 20 | nA | Data = 0x0000, TA = TA maximum | 3 | ||
| Full-Scale Gain Error | GFSE | -4 | 1 | 4 | mV | Data = 0xFFFF | 3 |
| VREF Range | VREF | -15 | 15 | V | 3 | ||
| Logic Input Low Voltage | VIL | 0.8 | V | 3 | |||
| Logic Input High Voltage | VIH | 2.4 | V | 3 | |||
| Input Leakage Current | IIL | 10 | µA | 3 | |||
| Input Capacitance | CIL | 10 | pF | 3 | |||
| Clock Width High | tCH | 10 | ns | See Figure 4 and Figure 5 | 3 | ||
| Clock Width Low | tCL | 10 | ns | See Figure 4 and Figure 5 | 3 | ||
| CS to Clock Setup | tCSS | 0 | ns | See Figure 4 and Figure 5 | 3 | ||
| Clock to CS Hold | tCSH | 10 | ns | See Figure 4 and Figure 5 | 3 | ||
| Data Setup | tDS | 5 | ns | See Figure 4 and Figure 5 | 3 | ||
| Data Hold | tDH | 10 | ns | See Figure 4 and Figure 5 | 3 | ||
| Power Supply Range | VDD | 4.5 | 5.5 | V | 5 V ± 10% | 3 | |
| Positive Supply Current | IDD | 10 | µA | Logic inputs = 0 V | 3 | ||
| Power Dissipation | PDISS | 0.055 | mW | Logic inputs = 0 V | 3 | ||
| Power Supply Sensitivity | PSS | 0.006 | %/% | ΔVDD = ±5% | 3 | ||
| Reference Input Resistance tolerance | RREF | -30 | 30 | % | 9 | ||
| VDD to GND | VDD | -0.3 | 8 | V | 5 | ||
| VREF to GND | VREF | -18 | 18 | V | 5 | ||
| Logic Inputs to GND | -0.3 | 8 | V | 5 | |||
| V(IOUT) to GND | V(IOUT) | -0.3 | V | Upper limit printed as VDD + 0.3 V | 5 | ||
| Input Current to Any Pin Except Supplies | -50 | 50 | mA | 5 | |||
| Maximum Junction Temperature | TJ Max | 150 | °C | 5 | |||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Operating Temperature Range | -40 | 85 | °C | Model B and Model C | 5 | ||
| Lead Temperature, vapor phase | 215 | °C | R-8, RM-8 (Vapor Phase, 60 sec) | 5 | |||
| Lead Temperature, infrared | 220 | °C | R-8, RM-8 (Infrared, 15 sec) | 5 | |||
| Thermal Resistance, junction-to-ambient (MSOP) | θJA | 150 | °C/W | 8-Lead Surface Mount (MSOP) | 5 | ||
| Full-Scale Temperature Coefficient | TCVFS | 1 | ppm/°C | 3 | |||
| Input Resistance | RREF | 5 | kΩ | 3 | |||
| Input Capacitance | CREF | 5 | pF | 3 | |||
| Output Current | IOUT | 2 | mA | Data = 0xFFFF for AD5543 | 3 | ||
| Output Capacitance | COUT | 200 | pF | Code dependent | 3 | ||
| Output Voltage Settling Time | tS | 0.5 | µs | To ±0.1% of full scale, Data = 0x0000 to 0xFFFF to 0x0000 for AD5543 | 4 | ||
| Reference Multiplying Bandwidth | BW | 6.6 | MHz | VREF = 100 mV rms, data = 0xFFFF | 4 | ||
| Total Harmonic Distortion | THD | -103 | dB | VREF = 5 V p-p, data = 0xFFFF, f = 1 kHz | 4 |
CAD (KiCad official)
- Symbol:
AD5543BRMZ - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
ad5543brmz-etched.step/ad5543brmz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5543brmz.step/ad5543brmz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
a05810efa01ae03e, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).