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AD5541BRZ

Analog Devices · Digital To Analog Converters (DACs) · SOIC-8

AD5541BRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output Analog output voltage from the DAC.
2 AGND power_in Ground reference point for analog circuitry.
3 REF input Voltage reference input for the DAC; connect to an external 2.5 V reference, which can range from 2 V to VDD.
4 CS input Logic input chip select signal used to frame the serial data input.
5 SCLK input Clock input; data is clocked into the input register on the rising edge of SCLK, with duty cycle between 40% and 60%.
6 DIN input Serial data input accepting 16-bit words, clocked into the input register on the rising edge of SCLK.
7 DGND power_in Digital ground, the ground reference for digital circuitry.
8 VDD power_in Analog supply voltage, 5 V ± 10%.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category ADC/DAC/Data Conversion
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL), B grade INL -2 0.5 2 LSB B, J grades 3
Differential Nonlinearity (DNL) DNL -1 0.5 1 LSB Guaranteed monotonic 3
Gain Error (25°C) -2 0.5 2 LSB TA = 25°C 3
Gain Error (over temperature) -3 3 LSB 3
Unipolar Zero Code Error (25°C) -0.7 0.3 0.7 LSB TA = 25°C 3
Unipolar Zero Code Error (over temperature) -1.5 1.5 LSB 3
Output Voltage Range, unipolar 0 V Unipolar operation; max VREF − 1 LSB 3
Reference Input Range 2 V max printed as VDD 3
Input Current -1 1 μA 3
Input Low Voltage VINL 0.8 V 3
Input High Voltage VINH 2.4 V 3
Supply Voltage VDD 2.7 5.5 V Digital inputs at rails 4
Supply Current IDD 125 150 μA Digital inputs at rails 4
Power Dissipation 0.625 0.825 mW Digital inputs at rails 4
SCLK cycle frequency fSCLK 25 MHz 4
SCLK cycle time t1 40 ns 4
SCLK high time t2 20 ns 4
SCLK low time t3 20 ns 4
CS low to SCLK high setup t4 10 ns 4
CS high to SCLK high setup t5 15 ns 4
SCLK high to CS low hold time t6 30 ns 4
SCLK high to CS high hold time t7 20 ns 4
Data setup time t8 15 ns 4
Data hold time t9 4 ns VINH = 90% of VDD, VINL = 10% of VDD 4
Data hold time t9 7.5 ns VINH = 3V, VINL = 0 V 4
CS high time between active periods t12 30 ns 4
VDD to AGND -0.3 6 V TA = 25°C 5
Digital Input Voltage to DGND -0.3 6 V max printed as VDD + 0.3 V 5
VOUT to AGND -0.3 6 V max printed as VDD + 0.3 V 5
AGND to DGND -0.3 0.3 V 5
Input Current to Any Pin Except Supplies -10 10 mA 5
Operating Temperature Range (Industrial, B version) -40 85 °C 5
Storage Temperature Range -65 150 °C 5
Maximum Junction Temperature TJ max 150 °C 5
Lead Temperature, Soldering Peak 260 °C As per JEDEC Standard 20 5
ESD (HBM) 5 kV HBM Classification 5
Thermal Impedance, SOIC (R-8) θJA 149.5 °C/W 5
Gain Error Temperature Coefficient 0.1 ppm/°C printed ±0.1 3
Unipolar Zero Code Temperature Coefficient 0.05 ppm/°C printed ±0.05 3
Output Voltage Settling Time 1 μs To 1/2 LSB of FS, CL = 10 pF 3
Slew Rate 17 V/μs CL = 10 pF, measured from 0% to 63% 3
Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around the major carry 3
Digital Feedthrough 0.2 nV-sec All 1s loaded to DAC, VREF = 2.5 V 3
DAC Output Impedance 6.25 kΩ Tolerance typically 20% 3
Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x8400, frequency = 1 kHz 3
Output Noise 0.134 µV p-p 0.1 Hz to 10 Hz 3
Power Supply Rejection Ratio 1 LSB ΔVDD ± 10% 3
Reference Input Resistance 9 kΩ Unipolar operation 3
Input Capacitance 10 pF 3
Hysteresis Voltage 0.15 V 3
Reference −3 dB Bandwidth 2.2 MHz All 1s loaded 3
Reference Feedthrough 1 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz 3
Signal-to-Noise Ratio 92 dB 3
Reference Input Capacitance 26 pF Code 0x0000 3

CAD (KiCad official)

  • Symbol: AD5541BRZ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ad5541brz-etched.step / ad5541brz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5541brz.step / ad5541brz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 6a9cdf0db0bc1b51, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF