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Ray Set visibility: public debd76d 3d ago
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{
  "schema_version": 1,
  "type": "component",
  "slug": "ad5512aacpz-reel7",
  "title": "AD5512AACPZ-REEL7",
  "brief": "Analog Devices Pre-ordered Chips, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "interface ics",
    "ad5512aacpz-reel7",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "AD5512AACPZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "LFCSP-16(3x3)",
    "pin_count": 17,
    "category": "Interface ICs",
    "subcategory": "Pre-ordered Chips",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf",
    "parts": {
      "symbol": "ad5512aacpz-reel7.kicad_sym",
      "footprint": "ad5512aacpz-reel7.kicad_mod",
      "model_3d": "ad5512aacpz-reel7-hero.glb",
      "model_3d_plain": "ad5512aacpz-reel7-etched.glb",
      "model_3d_step": "ad5512aacpz-reel7-etched.step",
      "model_3d_step_plain": "ad5512aacpz-reel7.step",
      "lbr": "ad5512aacpz-reel7.lbr"
    },
    "distributor_links": {
      "lcsc": "C649774",
      "digikey": "505-AD5512AACPZ-REEL7TR-ND",
      "mouser": "584-AD5512AACPZ-R7"
    },
    "distributor_check": {
      "checked_at": "2026-10-31T12:39:16Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD5512AACPZ-REEL7TR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD5512AACPZ-R7",
        "status": "found",
        "lifecycle": "Restricted Availability"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VOUT",
        "type": "output",
        "description": "Analog output voltage from the DAC."
      },
      {
        "number": "2",
        "name": "AGNDF",
        "type": "power_in",
        "description": "Ground reference point for analog circuitry (Force)."
      },
      {
        "number": "3",
        "name": "AGNDS",
        "type": "power_in",
        "description": "Ground reference point for analog circuitry (Sense)."
      },
      {
        "number": "4",
        "name": "REFS",
        "type": "input",
        "description": "Voltage reference input (Sense) for the DAC; connect to an external 2.5 V reference, which can range from 2 V to VDD."
      },
      {
        "number": "5",
        "name": "REFF",
        "type": "input",
        "description": "Voltage reference input (Force) for the DAC; connect to an external 2.5 V reference, which can range from 2 V to VDD."
      },
      {
        "number": "6",
        "name": "CS",
        "type": "input",
        "description": "Logic input chip select signal used to frame the serial data input."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect."
      },
      {
        "number": "8",
        "name": "SCLK",
        "type": "input",
        "description": "Clock input; data is clocked into the input register on the rising edge of SCLK, duty cycle must be between 40% and 60%."
      },
      {
        "number": "9",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input accepting 16-bit words, clocked into the input register on the rising edge of SCLK."
      },
      {
        "number": "10",
        "name": "CLR",
        "type": "input",
        "description": "Asynchronous clear input, falling edge sensitive; when low all LDAC pulses are ignored and when activated the DAC register is cleared to midscale."
      },
      {
        "number": "11",
        "name": "LDAC",
        "type": "input",
        "description": "When taken low, the DAC register is simultaneously updated with the contents of the input register."
      },
      {
        "number": "12",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground, ground reference for digital circuitry."
      },
      {
        "number": "13",
        "name": "INV",
        "type": "passive",
        "description": "Connection to the internal scaling resistors of the DAC; connect to the external op amp inverting input in bipolar mode."
      },
      {
        "number": "14",
        "name": "VLOGIC",
        "type": "power_in",
        "description": "Logic power supply (1.8 V to 5.5 V)."
      },
      {
        "number": "15",
        "name": "VDD",
        "type": "power_in",
        "description": "Analog supply voltage, 5 V ± 10% (2.7 V to 5.5 V operating range)."
      },
      {
        "number": "16",
        "name": "RFB",
        "type": "passive",
        "description": "Feedback resistor pin; in bipolar mode connect to the external op amp output."
      },
      {
        "number": "17",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Datasheet lists VDD as 5 V ± 10% in the pin table but 2.7 V to 5.5 V in specifications; description ; Exposed pad is numbered 'EPAD', not a numeric pin; type assigned as power_in (GND) per datasheet not; Pin types for INV and RFB (passive) are inferred from their function as resistor-network connections"
        ],
        "pages_sent": 10,
        "cost_usd": 0.124,
        "at": "2026-10-31T12:38:58"
      },
      "datasheet": {
        "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf",
        "pages": 21,
        "sha256": "8ad00fec331dde5f",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ad5512aacpz-reel7.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3,
          3,
          0.785
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ad5512aacpz-reel7-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3,
          3,
          0.785
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "ef2559ab2a421f9bc9c0c1218e1e49e4417b8b58c4b7a44c645cb97df00d5a49",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "CP-16-22",
      "source_page": 20,
      "D": {
        "nom_mm": 3,
        "range_mm": [
          2.9,
          3.1
        ]
      },
      "E1": {
        "nom_mm": 3,
        "range_mm": [
          2.9,
          3.1
        ]
      },
      "e": {
        "nom_mm": 0.5,
        "range_mm": [
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          null
        ]
      },
      "A": {
        "nom_mm": 0.75,
        "range_mm": [
          0.7,
          0.8
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "ad5512aacpz-reel7.step",
        "verdict": "PASS",
        "reasons": [
          "height within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "LFCSP-16(3x3)",
      "Category": "Interface ICs",
      "Pins": "17"
    },
    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "datasheet_sha256": "8ad00fec331dde5fbd88bccd41899c386a05fee5f4828d9ce3d6ef5166e5903c",
      "rows": [
        {
          "name": "Relative Accuracy (INL)",
          "symbol": "INL",
          "kind": "electrical",
          "unit": "LSB",
          "min": -1,
          "typ": 0.5,
          "max": 1,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Differential Nonlinearity (DNL)",
          "symbol": "DNL",
          "kind": "electrical",
          "unit": "LSB",
          "min": -1,
          "typ": 0.5,
          "max": 1,
          "conditions": "Guaranteed monotonic",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Gain Error",
          "symbol": "",
          "kind": "electrical",
          "unit": "LSB",
          "min": -2,
          "typ": 0.5,
          "max": 2,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Unipolar Zero-Code Error",
          "symbol": "",
          "kind": "electrical",
          "unit": "LSB",
          "min": -0.5,
          "typ": 0.03,
          "max": 0.5,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Bipolar Resistor Matching Ratio Error",
          "symbol": "",
          "kind": "electrical",
          "unit": "%",
          "min": -0.08,
          "typ": 0.02,
          "max": 0.08,
          "conditions": "Ratio error",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Bipolar Zero Offset Error",
          "symbol": "",
          "kind": "electrical",
          "unit": "LSB",
          "min": -2,
          "typ": 0.07,
          "max": 2,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
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        {
          "name": "Bipolar Zero-Code Offset Error",
          "symbol": "",
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          "min": -0.5,
          "typ": 0.02,
          "max": 0.5,
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          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Bipolar Gain Error",
          "symbol": "",
          "kind": "electrical",
          "unit": "LSB",
          "min": -2,
          "typ": 0.07,
          "max": 2,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Output Voltage Range (unipolar)",
          "symbol": "",
          "kind": "electrical",
          "unit": "V",
          "min": 0,
          "typ": null,
          "max": null,
          "conditions": "Unipolar operation; max = VREF − 1 LSB",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Reference Input Range",
          "symbol": "",
          "kind": "electrical",
          "unit": "V",
          "min": 2,
          "typ": null,
          "max": null,
          "conditions": "max = VDD",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Logic Input Current",
          "symbol": "",
          "kind": "electrical",
          "unit": "μA",
          "min": -1,
          "typ": null,
          "max": 1,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Input Low Voltage",
          "symbol": "VINL",
          "kind": "electrical",
          "unit": "V",
          "min": null,
          "typ": null,
          "max": 0.8,
          "conditions": "VDD = 2.7 V to 5.5 V",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Input High Voltage",
          "symbol": "VINH",
          "kind": "electrical",
          "unit": "V",
          "min": 2.4,
          "typ": null,
          "max": null,
          "conditions": "VDD = 2.7 V to 5.5 V",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Supply Voltage",
          "symbol": "VDD",
          "kind": "electrical",
          "unit": "V",
          "min": 2.7,
          "typ": null,
          "max": 5.5,
          "conditions": "All digital inputs at 0 V, VLOGIC, or VDD",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Supply Current",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "µA",
          "min": null,
          "typ": 125,
          "max": 150,
          "conditions": "VIH = VLOGIC or VDD and VIL = GND",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Logic Supply Voltage",
          "symbol": "VLOGIC",
          "kind": "electrical",
          "unit": "V",
          "min": 1.8,
          "typ": null,
          "max": 5.5,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Logic Supply Current",
          "symbol": "ILOGIC",
          "kind": "electrical",
          "unit": "µA",
          "min": null,
          "typ": 15,
          "max": 24,
          "conditions": "All digital inputs at 0 V, VLOGIC, or VDD",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "Power Dissipation",
          "symbol": "",
          "kind": "electrical",
          "unit": "mW",
          "min": null,
          "typ": 1.5,
          "max": 6.05,
          "conditions": "",
          "source_page": 3,
          "source": "datasheet"
        },
        {
          "name": "SCLK cycle frequency",
          "symbol": "fSCLK",
          "kind": "timing",
          "unit": "MHz",
          "min": null,
          "typ": null,
          "max": 50,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "SCLK cycle time",
          "symbol": "t1",
          "kind": "timing",
          "unit": "ns",
          "min": 20,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "SCLK high time",
          "symbol": "t2",
          "kind": "timing",
          "unit": "ns",
          "min": 10,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "SCLK low time",
          "symbol": "t3",
          "kind": "timing",
          "unit": "ns",
          "min": 10,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "CS low to SCLK high setup",
          "symbol": "t4",
          "kind": "timing",
          "unit": "ns",
          "min": 5,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "CS high to SCLK high setup",
          "symbol": "t5",
          "kind": "timing",
          "unit": "ns",
          "min": 5,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "SCLK high to CS low hold time",
          "symbol": "t6",
          "kind": "timing",
          "unit": "ns",
          "min": 5,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "SCLK high to CS high hold time",
          "symbol": "t7",
          "kind": "timing",
          "unit": "ns",
          "min": 5,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "Data setup time",
          "symbol": "t8",
          "kind": "timing",
          "unit": "ns",
          "min": 10,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
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          "source": "datasheet"
        },
        {
          "name": "Data hold time",
          "symbol": "t9",
          "kind": "timing",
          "unit": "ns",
          "min": 4,
          "typ": null,
          "max": null,
          "conditions": "VINH = 90% of VDD, VINL = 10% of VDD; 2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "LDAC pulsewidth",
          "symbol": "t10",
          "kind": "timing",
          "unit": "ns",
          "min": 20,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "CS high to LDAC low setup",
          "symbol": "t11",
          "kind": "timing",
          "unit": "ns",
          "min": 10,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "CS high time between active periods",
          "symbol": "t12",
          "kind": "timing",
          "unit": "ns",
          "min": 15,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "CLR pulsewidth",
          "symbol": "t13",
          "kind": "timing",
          "unit": "ns",
          "min": 15,
          "typ": null,
          "max": null,
          "conditions": "2.7 V ≤ VLOGIC ≤ 5.5 V",
          "source_page": 6,
          "source": "datasheet"
        },
        {
          "name": "VDD to AGND",
          "symbol": "",
          "kind": "absolute_maximum",
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          "typ": 92,
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