# AD5512AACPZ-REEL7

**Analog Devices** · Pre-ordered Chips · LFCSP-16(3x3)

AD5512AACPZ-REEL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output voltage from the DAC. |
| 2 | AGNDF | power_in | Ground reference point for analog circuitry (Force). |
| 3 | AGNDS | power_in | Ground reference point for analog circuitry (Sense). |
| 4 | REFS | input | Voltage reference input (Sense) for the DAC; connect to an external 2.5 V reference, which can range from 2 V to VDD. |
| 5 | REFF | input | Voltage reference input (Force) for the DAC; connect to an external 2.5 V reference, which can range from 2 V to VDD. |
| 6 | CS | input | Logic input chip select signal used to frame the serial data input. |
| 7 | NC | unconnected | No connect. |
| 8 | SCLK | input | Clock input; data is clocked into the input register on the rising edge of SCLK, duty cycle must be between 40% and 60%. |
| 9 | DIN | input | Serial data input accepting 16-bit words, clocked into the input register on the rising edge of SCLK. |
| 10 | CLR | input | Asynchronous clear input, falling edge sensitive; when low all LDAC pulses are ignored and when activated the DAC register is cleared to midscale. |
| 11 | LDAC | input | When taken low, the DAC register is simultaneously updated with the contents of the input register. |
| 12 | DGND | power_in | Digital ground, ground reference for digital circuitry. |
| 13 | INV | passive | Connection to the internal scaling resistors of the DAC; connect to the external op amp inverting input in bipolar mode. |
| 14 | VLOGIC | power_in | Logic power supply (1.8 V to 5.5 V). |
| 15 | VDD | power_in | Analog supply voltage, 5 V ± 10% (2.7 V to 5.5 V operating range). |
| 16 | RFB | passive | Feedback resistor pin; in bipolar mode connect to the external op amp output. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | Interface ICs |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL) | INL | -1 | 0.5 | 1 | LSB |  | 3 |
| Differential Nonlinearity (DNL) | DNL | -1 | 0.5 | 1 | LSB | Guaranteed monotonic | 3 |
| Gain Error |  | -2 | 0.5 | 2 | LSB |  | 3 |
| Unipolar Zero-Code Error |  | -0.5 | 0.03 | 0.5 | LSB |  | 3 |
| Bipolar Resistor Matching Ratio Error |  | -0.08 | 0.02 | 0.08 | % | Ratio error | 3 |
| Bipolar Zero Offset Error |  | -2 | 0.07 | 2 | LSB |  | 3 |
| Bipolar Zero-Code Offset Error |  | -0.5 | 0.02 | 0.5 | LSB |  | 3 |
| Bipolar Gain Error |  | -2 | 0.07 | 2 | LSB |  | 3 |
| Output Voltage Range (unipolar) |  | 0 |  |  | V | Unipolar operation; max = VREF − 1 LSB | 3 |
| Reference Input Range |  | 2 |  |  | V | max = VDD | 3 |
| Logic Input Current |  | -1 |  | 1 | μA |  | 3 |
| Input Low Voltage | VINL |  |  | 0.8 | V | VDD = 2.7 V to 5.5 V | 3 |
| Input High Voltage | VINH | 2.4 |  |  | V | VDD = 2.7 V to 5.5 V | 3 |
| Supply Voltage | VDD | 2.7 |  | 5.5 | V | All digital inputs at 0 V, VLOGIC, or VDD | 3 |
| Supply Current | IDD |  | 125 | 150 | µA | VIH = VLOGIC or VDD and VIL = GND | 3 |
| Logic Supply Voltage | VLOGIC | 1.8 |  | 5.5 | V |  | 3 |
| Logic Supply Current | ILOGIC |  | 15 | 24 | µA | All digital inputs at 0 V, VLOGIC, or VDD | 3 |
| Power Dissipation |  |  | 1.5 | 6.05 | mW |  | 3 |
| SCLK cycle frequency | fSCLK |  |  | 50 | MHz | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| SCLK cycle time | t1 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| SCLK high time | t2 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| SCLK low time | t3 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| CS low to SCLK high setup | t4 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| CS high to SCLK high setup | t5 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| SCLK high to CS low hold time | t6 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| SCLK high to CS high hold time | t7 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| Data setup time | t8 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| Data hold time | t9 | 4 |  |  | ns | VINH = 90% of VDD, VINL = 10% of VDD; 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| LDAC pulsewidth | t10 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| CS high to LDAC low setup | t11 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| CS high time between active periods | t12 | 15 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| CLR pulsewidth | t13 | 15 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 |
| VDD to AGND |  | -0.3 |  | 6 | V | TA = 25°C | 7 |
| Digital Input Voltage to DGND |  | -0.3 |  |  | V | max = VDD + 0.3 V | 7 |
| VOUT to AGND |  | -0.3 |  |  | V | max = VDD + 0.3 V | 7 |
| AGNDF, AGNDS to DGND |  | -0.3 |  | 0.3 | V |  | 7 |
| Input Current to Any Pin Except Supplies |  | -10 |  | 10 | mA |  | 7 |
| Operating Temperature Range (A Version) |  | -40 |  | 125 | °C | AD5512A Industrial | 7 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 7 |
| Maximum Junction Temperature | TJ max |  |  | 150 | °C |  | 7 |
| Lead Temperature, Soldering Peak |  |  |  | 260 | °C | As per JEDEC Standard 20 | 7 |
| ESD (HBM) |  |  |  | 5 | kV | HBM classification | 7 |
| Thermal Impedance, LFCSP (CP-16-22) | θJA |  | 73 |  | °C/W | LFCSP (CP-16-22) | 7 |
| Resolution |  |  | 12 |  | Bits |  | 3 |
| Gain Error Temperature Coefficient |  |  | 0.1 |  | ppm/°C | ±0.1 | 3 |
| Unipolar Zero-Code Temperature Coefficient |  |  | 0.05 |  | ppm/°C | ±0.05 | 3 |
| Bipolar Zero Temperature Coefficient |  |  | 0.2 |  | ppm/°C | ±0.2 | 3 |
| Bipolar Gain Temperature Coefficient |  |  | 0.1 |  | ppm/°C | ±0.1 | 3 |
| DAC Output Impedance |  |  | 6.25 |  | kΩ | Tolerance typically 20% | 3 |
| Output Noise Spectral Density |  |  | 11.8 |  | nV/√Hz | DAC code = 0x840 (AD5512A), frequency = 1 kHz, unipolar mode | 3 |
| Output Noise |  |  | 0.134 |  | μV p-p | 0.1 Hz to 10 Hz, unipolar mode | 3 |
| Reference Input Resistance (unipolar) |  |  | 9 |  | kΩ | Unipolar operation | 3 |
| Reference Input Resistance (bipolar) |  |  | 7.5 |  | kΩ | Bipolar operation | 3 |
| Reference Input Capacitance |  |  | 26 |  | pF | Code 0x0000 | 3 |
| Power Supply Rejection Ratio |  |  | 1 |  | LSB | ΔVDD ± 10% | 3 |
| Bipolar Resistor Matching | RFB/RINV |  | 1 |  | Ω/Ω | typically RFB = RINV = 28 kΩ | 3 |
| Output Voltage Settling Time |  |  | 1 |  | μs | To 1/2 LSB of FS, CL = 10 pF | 5 |
| Slew Rate |  |  | 17 |  | V/µs | CL = 10 pF, measured from 0% to 63% | 5 |
| Digital-to-Analog Glitch Impulse |  |  | 1.1 |  | nV-sec | 1 LSB change around major carry | 5 |
| Signal-to-Noise Ratio |  |  | 92 |  | dB |  | 5 |

## CAD (KiCad official)

- Symbol: `AD5512AACPZ-REEL7`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `ad5512aacpz-reel7-etched.step` / `ad5512aacpz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5512aacpz-reel7.step` / `ad5512aacpz-reel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf) (21 pp, sha256 `8ad00fec331dde5f`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5512aacpz-reel7-datasheet.pdf)