component
AD5453YUJZ-REEL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5453YUJZ-REEL7
Analog Devices · Digital To Analog Converters (DACs) · TSOT-23-8
AD5453YUJZ-REEL7 from Analog Devices, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFB | passive | DAC feedback resistor (RFB, 7 kΩ min / 9 kΩ typ / 11 kΩ max) that sets the voltage output when connected to the external amplifier output. |
| 2 | VREF | power_in | DAC reference voltage input, which accepts a reference range of ±10 V. |
| 3 | VDD | power_in | Positive power supply input that operates from 2.5 V to 5.5 V. |
| 4 | SYNC | input | Active-low frame synchronization input that loads data into the shift register on the active edge of the following clocks; logic inputs are clamped by internal diodes and limited to −0.3 V to VDD + 0.3 V. |
| 5 | SDIN | input | Serial data input clocked into the 16-bit input register, sampled on the falling SCLK edge by default (rising edge selectable via control bits); logic inputs are limited to −0.3 V to VDD + 0.3 V. |
| 6 | SCLK | input | Serial clock input that clocks data into the input shift register on the falling edge by default (rising edge selectable), supporting up to 50 MHz serial interface operation. |
| 7 | GND | power_in | Ground pin for the device; VDD to GND is rated −0.3 V to +7 V. |
| 8 | IOUT1 | output | DAC current output, with IOUT1 to GND rated −0.3 V to +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-23-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | -2 | 2 | LSB | 3 | |||
| Differential Nonlinearity | -1 | 2 | LSB | Guaranteed monotonic | 3 | ||
| Total Unadjusted Error | -4 | 4 | LSB | 3 | |||
| Gain Error | -2.5 | 2.5 | LSB | 3 | |||
| Gain Error Temperature Coefficient | -2 | 2 | ppm FSR/°C | 3 | |||
| Output Leakage Current | -1 | 1 | nA | Data = 0x0000, TA = 25°C, IOUT1 | 3 | ||
| Output Leakage Current | -10 | 10 | nA | Data = 0x0000, TA = −40°C to +125°C, IOUT1 | 3 | ||
| VREF Input Resistance | 7 | 9 | 11 | kΩ | Input resistance, TC = −50 ppm/°C | 3 | |
| RFB Feedback Resistance | 7 | 9 | 11 | kΩ | Input resistance, TC = −50 ppm/°C | 3 | |
| Input Capacitance, Zero-Scale Code | 18 | 22 | pF | 3 | |||
| Input Capacitance, Full-Scale Code | 18 | 22 | pF | 3 | |||
| Input High Voltage | VIH | 2 | V | VDD = 3.6 V to 5 V | 3 | ||
| Input High Voltage | VIH | 1.7 | V | VDD = 2.5 V to 3.6 V | 3 | ||
| Input Low Voltage | VIL | 0.8 | V | VDD = 2.7 V to 5.5 V | 3 | ||
| Input Low Voltage | VIL | 0.7 | V | VDD = 2.5 V to 2.7 V | 3 | ||
| Output Low Voltage | VOL | 0.4 | V | VDD = 4.5 V to 5 V, ISINK = 200 μA | 3 | ||
| Input Leakage Current | IIL | -1 | 1 | μA | TA = 25°C | 3 | |
| Input Leakage Current | IIL | -10 | 10 | μA | TA = −40°C to +125°C | 3 | |
| Output Voltage Settling Time (to ±1 mV of FS) | 100 | 110 | ns | VREF = 10 V, RLOAD = 100 Ω; measured to ±1 mV of FS | 4 | ||
| Output Voltage Settling Time (to ±4 mV of FS) | 24 | 40 | ns | VREF = 10 V, RLOAD = 100 Ω; measured to ±4 mV of FS | 4 | ||
| Output Voltage Settling Time (to ±16 mV of FS) | 16 | 33 | ns | VREF = 10 V, RLOAD = 100 Ω; measured to ±16 mV of FS | 4 | ||
| Digital Delay | 20 | 40 | ns | Interface delay time | 4 | ||
| 10% to 90% Settling Time | 10 | 30 | ns | Rise and fall times, VREF = 10 V, RLOAD = 100 Ω | 4 | ||
| Power Supply Range | 2.5 | 5.5 | V | 4 | |||
| IDD | IDD | 0.4 | 10 | μA | TA = −40°C to +125°C, logic inputs = 0 V or VDD | 4 | |
| IDD | IDD | 0.6 | μA | TA = 25°C, logic inputs = 0 V or VDD | 4 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| VREF, RFB to GND | -12 | 12 | V | 6 | |||
| IOUT1 to GND | IOUT1 | -0.3 | 7 | V | 6 | ||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | 6 | |||
| Logic Inputs and Output (maximum printed as VDD + 0.3 V) | -0.3 | V | 6 | ||||
| Operating Temperature Range, Extended (Y Version) | -40 | 125 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| θJA Thermal Impedance, 8-Lead TSOT | θJA | 211 | °C/W | 8-lead TSOT | 6 | ||
| Lead Temperature, Soldering | 300 | °C | 10 sec | 6 | |||
| IR Reflow, Peak Temperature | 235 | °C | <20 sec | 6 | |||
| Maximum clock frequency | fSCLK | 50 | MHz | VDD = 2.5 V to 5.5 V | 5 | ||
| SCLK cycle time | t1 | 20 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| SCLK high time | t2 | 8 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| SCLK low time | t3 | 8 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| SYNC falling edge to SCLK active edge setup time | t4 | 8 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| Data setup time | t5 | 5 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| Data hold time | t6 | 4.5 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| SYNC rising edge to SCLK active edge | t7 | 5 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| Minimum SYNC high time | t8 | 30 | ns | VDD = 2.5 V to 5.5 V | 5 |
CAD (KiCad official)
- Symbol:
AD5453YUJZ-REEL7 - Footprint:
Package_TO_SOT_SMD:TSOT-23-8 - 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files:
ad5453yujz-reel7-etched.step/ad5453yujz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5453yujz-reel7.step/ad5453yujz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
6be2f2663e55e3c1, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5453YUJZ-REEL7
**Analog Devices** · Digital To Analog Converters (DACs) · TSOT-23-8
AD5453YUJZ-REEL7 from Analog Devices, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFB | passive | DAC feedback resistor (RFB, 7 kΩ min / 9 kΩ typ / 11 kΩ max) that sets the voltage output when connected to the external amplifier output. |
| 2 | VREF | power_in | DAC reference voltage input, which accepts a reference range of ±10 V. |
| 3 | VDD | power_in | Positive power supply input that operates from 2.5 V to 5.5 V. |
| 4 | SYNC | input | Active-low frame synchronization input that loads data into the shift register on the active edge of the following clocks; logic inputs are clamped by internal diodes and limited to −0.3 V to VDD + 0.3 V. |
| 5 | SDIN | input | Serial data input clocked into the 16-bit input register, sampled on the falling SCLK edge by default (rising edge selectable via control bits); logic inputs are limited to −0.3 V to VDD + 0.3 V. |
| 6 | SCLK | input | Serial clock input that clocks data into the input shift register on the falling edge by default (rising edge selectable), supporting up to 50 MHz serial interface operation. |
| 7 | GND | power_in | Ground pin for the device; VDD to GND is rated −0.3 V to +7 V. |
| 8 | IOUT1 | output | DAC current output, with IOUT1 to GND rated −0.3 V to +7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-23-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | | -2 | | 2 | LSB | | 3 |
| Differential Nonlinearity | | -1 | | 2 | LSB | Guaranteed monotonic | 3 |
| Total Unadjusted Error | | -4 | | 4 | LSB | | 3 |
| Gain Error | | -2.5 | | 2.5 | LSB | | 3 |
| Gain Error Temperature Coefficient | | -2 | | 2 | ppm FSR/°C | | 3 |
| Output Leakage Current | | -1 | | 1 | nA | Data = 0x0000, TA = 25°C, IOUT1 | 3 |
| Output Leakage Current | | -10 | | 10 | nA | Data = 0x0000, TA = −40°C to +125°C, IOUT1 | 3 |
| VREF Input Resistance | | 7 | 9 | 11 | kΩ | Input resistance, TC = −50 ppm/°C | 3 |
| RFB Feedback Resistance | | 7 | 9 | 11 | kΩ | Input resistance, TC = −50 ppm/°C | 3 |
| Input Capacitance, Zero-Scale Code | | | 18 | 22 | pF | | 3 |
| Input Capacitance, Full-Scale Code | | | 18 | 22 | pF | | 3 |
| Input High Voltage | VIH | 2 | | | V | VDD = 3.6 V to 5 V | 3 |
| Input High Voltage | VIH | 1.7 | | | V | VDD = 2.5 V to 3.6 V | 3 |
| Input Low Voltage | VIL | | | 0.8 | V | VDD = 2.7 V to 5.5 V | 3 |
| Input Low Voltage | VIL | | | 0.7 | V | VDD = 2.5 V to 2.7 V | 3 |
| Output Low Voltage | VOL | | | 0.4 | V | VDD = 4.5 V to 5 V, ISINK = 200 μA | 3 |
| Input Leakage Current | IIL | -1 | | 1 | μA | TA = 25°C | 3 |
| Input Leakage Current | IIL | -10 | | 10 | μA | TA = −40°C to +125°C | 3 |
| Output Voltage Settling Time (to ±1 mV of FS) | | | 100 | 110 | ns | VREF = 10 V, RLOAD = 100 Ω; measured to ±1 mV of FS | 4 |
| Output Voltage Settling Time (to ±4 mV of FS) | | | 24 | 40 | ns | VREF = 10 V, RLOAD = 100 Ω; measured to ±4 mV of FS | 4 |
| Output Voltage Settling Time (to ±16 mV of FS) | | | 16 | 33 | ns | VREF = 10 V, RLOAD = 100 Ω; measured to ±16 mV of FS | 4 |
| Digital Delay | | | 20 | 40 | ns | Interface delay time | 4 |
| 10% to 90% Settling Time | | | 10 | 30 | ns | Rise and fall times, VREF = 10 V, RLOAD = 100 Ω | 4 |
| Power Supply Range | | 2.5 | | 5.5 | V | | 4 |
| IDD | IDD | | 0.4 | 10 | μA | TA = −40°C to +125°C, logic inputs = 0 V or VDD | 4 |
| IDD | IDD | | 0.6 | | μA | TA = 25°C, logic inputs = 0 V or VDD | 4 |
| VDD to GND | VDD | -0.3 | | 7 | V | | 6 |
| VREF, RFB to GND | | -12 | | 12 | V | | 6 |
| IOUT1 to GND | IOUT1 | -0.3 | | 7 | V | | 6 |
| Input Current to Any Pin Except Supplies | | -10 | | 10 | mA | | 6 |
| Logic Inputs and Output (maximum printed as VDD + 0.3 V) | | -0.3 | | | V | | 6 |
| Operating Temperature Range, Extended (Y Version) | | -40 | | 125 | °C | | 6 |
| Storage Temperature Range | | -65 | | 150 | °C | | 6 |
| Junction Temperature | | | | 150 | °C | | 6 |
| θJA Thermal Impedance, 8-Lead TSOT | θJA | | 211 | | °C/W | 8-lead TSOT | 6 |
| Lead Temperature, Soldering | | | | 300 | °C | 10 sec | 6 |
| IR Reflow, Peak Temperature | | | | 235 | °C | <20 sec | 6 |
| Maximum clock frequency | fSCLK | | | 50 | MHz | VDD = 2.5 V to 5.5 V | 5 |
| SCLK cycle time | t1 | 20 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
| SCLK high time | t2 | 8 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
| SCLK low time | t3 | 8 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
| SYNC falling edge to SCLK active edge setup time | t4 | 8 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
| Data setup time | t5 | 5 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
| Data hold time | t6 | 4.5 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
| SYNC rising edge to SCLK active edge | t7 | 5 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
| Minimum SYNC high time | t8 | 30 | | | ns | VDD = 2.5 V to 5.5 V | 5 |
## CAD (KiCad official)
- Symbol: `AD5453YUJZ-REEL7`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-8`
- 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files: `ad5453yujz-reel7-etched.step` / `ad5453yujz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5453yujz-reel7.step` / `ad5453yujz-reel7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ad5450_5451_5452_5453.pdf) (28 pp, sha256 `6be2f2663e55e3c1`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5453yujz-reel7-datasheet.pdf)