# AD5450YUJZ-REEL7

**Analog Devices** · Digital To Analog Converters (DAC) · TSOT-23-8

AD5450YUJZ-REEL7 from Analog Devices, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFB | passive | DAC feedback resistor, connected to the external amplifier output to establish the DAC voltage output. |
| 2 | VREF | power_in | DAC reference voltage input, with a reference input range of ±10 V. |
| 3 | VDD | power_in | Positive power supply input, operating from 2.5 V to 5.5 V. |
| 4 | SYNC | input | Active-low control input and frame synchronization signal for the input data; data is loaded to the shift register upon the active edge of the following clocks. |
| 5 | SDIN | input | Serial data input, clocked into the 16-bit input register on the active edge of SCLK; defaults to the falling edge, which the control bits can change to the rising edge. |
| 6 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge by default, or on the rising edge if set by the serial control bits. |
| 7 | GND | power_in | Ground pin. |
| 8 | IOUT1 | output | DAC current output. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-23-8 |
| Category | Data Acquisition |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy |  | -0.25 |  | 0.25 | LSB |  | 3 |
| Differential Nonlinearity |  | -0.5 |  | 0.5 | LSB | Guaranteed monotonic | 3 |
| Total Unadjusted Error |  | -0.5 |  | 0.5 | LSB |  | 3 |
| Gain Error |  | -0.25 |  | 0.25 | LSB |  | 3 |
| Gain Error Temperature Coefficient |  | -2 |  | 2 | ppm FSR/°C |  | 3 |
| Output Leakage Current |  | -1 |  | 1 | nA | Data = 0x0000, TA = 25°C, IOUT1 | 3 |
| Output Leakage Current |  | -10 |  | 10 | nA | Data = 0x0000, TA = −40°C to +125°C, IOUT1 | 3 |
| Reference Input Range |  | -10 |  | 10 | V |  | 3 |
| VREF Input Resistance |  | 7 | 9 | 11 | kΩ | Input resistance, TC = −50 ppm/°C | 3 |
| RFB Feedback Resistance |  | 7 | 9 | 11 | kΩ | Input resistance, TC = −50 ppm/°C | 3 |
| Input High Voltage | VIH | 2 |  |  | V | VDD = 3.6 V to 5 V | 3 |
| Input High Voltage | VIH | 1.7 |  |  | V | VDD = 2.5 V to 3.6 V | 3 |
| Input Low Voltage | VIL |  |  | 0.8 | V | VDD = 2.7 V to 5.5 V | 3 |
| Input Low Voltage | VIL |  |  | 0.7 | V | VDD = 2.5 V to 2.7 V | 3 |
| Output Low Voltage | VOL |  |  | 0.4 | V | VDD = 4.5 V to 5 V, ISINK = 200 µA | 3 |
| Input Leakage Current | IIL | -1 |  | 1 | nA | TA = 25°C | 3 |
| Input Leakage Current | IIL | -10 |  | 10 | nA | TA = −40°C to +125°C | 3 |
| Power Supply Range |  | 2.5 |  | 5.5 | V |  | 4 |
| Supply Current | IDD |  | 0.4 | 10 | µA | TA = −40°C to +125°C, logic inputs = 0 V or VDD | 4 |
| Maximum Clock Frequency | fSCLK |  |  | 50 | MHz | VDD = 2.5 V to 5.5 V | 5 |
| SCLK Cycle Time | t1 | 20 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| SCLK High Time | t2 | 8 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| SCLK Low Time | t3 | 8 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| SYNC Falling Edge to SCLK Active Edge Setup Time | t4 | 8 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| Data Setup Time | t5 | 5 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| Data Hold Time | t6 | 4.5 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| SYNC Rising Edge to SCLK Active Edge | t7 | 5 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| Minimum SYNC High Time | t8 | 30 |  |  | ns | VDD = 2.5 V to 5.5 V | 5 |
| VDD to GND |  | -0.3 |  | 7 | V |  | 6 |
| VREF, RFB to GND |  | -12 |  | 12 | V |  | 6 |
| IOUT1 to GND |  | -0.3 |  | 7 | V |  | 6 |
| Input Current to Any Pin Except Supplies |  | -10 |  | 10 | mA |  | 6 |
| Logic Inputs and Output |  | -0.3 |  |  | V | Maximum VDD + 0.3 V | 6 |
| Operating Temperature Range, Extended (Y Version) |  | -40 |  | 125 | °C |  | 6 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 6 |
| Junction Temperature |  |  |  | 150 | °C |  | 6 |
| Lead Temperature, Soldering |  |  |  | 300 | °C | 10 sec | 6 |
| IR Reflow, Peak Temperature |  |  |  | 235 | °C | <20 sec | 6 |
| θJA Thermal Impedance, 8-Lead TSOT | θJA |  |  | 211 | °C/W | 8-lead TSOT | 6 |

## CAD (KiCad official)

- Symbol: `AD5450YUJZ-REEL7`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-8`
- 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files: `ad5450yujz-reel7-etched.step` / `ad5450yujz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5450yujz-reel7.step` / `ad5450yujz-reel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914613316964352) (28 pp, sha256 `7c6a87f60ca93e34`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5450yujz-reel7-datasheet.pdf)