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Ray Set visibility: public 5df862b 3d ago
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{
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  "type": "component",
  "slug": "ad5446yrmz",
  "title": "AD5446YRMZ",
  "brief": "Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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  "component": {
    "mpn": "AD5446YRMZ",
    "manufacturer": "Analog Devices",
    "package": "MSOP-10",
    "pin_count": 10,
    "category": "Data Converters",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5444_5446.pdf",
    "parts": {
      "symbol": "ad5446yrmz.kicad_sym",
      "footprint": "ad5446yrmz.kicad_mod",
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      "model_3d_plain": "ad5446yrmz-etched.glb",
      "model_3d_step": "ad5446yrmz-etched.step",
      "model_3d_step_plain": "ad5446yrmz.step",
      "lbr": "ad5446yrmz.lbr"
    },
    "distributor_links": {
      "lcsc": "C461537",
      "digikey": "505-AD5446YRMZ-ND",
      "mouser": "584-AD5446YRMZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T12:07:06Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD5446YRMZ-ND",
        "status": "found"
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      "mouser": {
        "pn": "584-AD5446YRMZ",
        "status": "found",
        "lifecycle": "Restricted Availability"
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    },
    "pins": [
      {
        "number": "1",
        "name": "IOUT1",
        "type": "output",
        "description": "DAC current output."
      },
      {
        "number": "2",
        "name": "IOUT2",
        "type": "passive",
        "description": "DAC analog ground, which should normally be tied to the analog ground of the system."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "4",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input; data is clocked into the input shift register on the falling edge by default, or on the rising edge if configured via the serial control bits."
      },
      {
        "number": "5",
        "name": "SDIN",
        "type": "input",
        "description": "Serial data input; data is clocked into the 16-bit input register on the active edge of the serial clock, falling edge by default on power-up."
      },
      {
        "number": "6",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input; when taken low data is loaded to the shift register on the active clock edges, and the output updates on the rising edge of SYNC."
      },
      {
        "number": "7",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output for daisy-chaining several parts; by default data is clocked out on the rising edge of SCLK, always on the alternate edge to data loaded into the shift register."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive power supply input, operable from 2.5 V to 5.5 V."
      },
      {
        "number": "9",
        "name": "VREF",
        "type": "power_in",
        "description": "DAC reference voltage input, with a ±10 V reference input range."
      },
      {
        "number": "10",
        "name": "RFB",
        "type": "passive",
        "description": "DAC feedback resistor that establishes the voltage output by connecting to an external amplifier output."
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    ],
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        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
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        "pages_sent": 8,
        "cost_usd": 0.0724,
        "at": "2026-10-30T12:06:50"
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      "datasheet": {
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        "pages": 25,
        "sha256": "df4ce99d21387139",
        "source_tier": "mfr"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 10,
        "described": 10,
        "cites_pages": true,
        "refuses_to_fabricate": true
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    "viewers": {
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      "footprint": "viewers/footprint.html"
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    "models_3d": [
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        "sha256": "b8f88eac3ce221c2ccb0b5048f9ad49c2ef4af148f8ae50c4e232e357683f547",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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      {
        "file": "ad5446yrmz-etched.step",
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        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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  },
  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "MSOP-10",
      "Category": "Data Converters",
      "Pins": "10"
    },
    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "datasheet_sha256": "df4ce99d21387139c0d16946a8394bc1d4210c30966a0863aa496e7552867d28",
      "rows": [
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          "name": "Resolution (AD5446)",
          "symbol": "",
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          "unit": "Bits",
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          "typ": 14,
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          "name": "Relative Accuracy",
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          "unit": "LSB",
          "min": -2,
          "typ": null,
          "max": 2,
          "conditions": "AD5446",
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          "source": "datasheet"
        },
        {
          "name": "Differential Nonlinearity",
          "symbol": "DNL",
          "kind": "electrical",
          "unit": "LSB",
          "min": -1,
          "typ": null,
          "max": 2,
          "conditions": "AD5446, guaranteed monotonic",
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          "source": "datasheet"
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        {
          "name": "Total Unadjusted Error",
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          "unit": "LSB",
          "min": -2.5,
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        {
          "name": "Gain Error Temperature Coefficient",
          "symbol": "",
          "kind": "temperature_coefficient",
          "unit": "ppm FSR/°C",
          "min": null,
          "typ": 2,
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        {
          "name": "Output Leakage Current",
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          "kind": "electrical",
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          "min": -1,
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          "conditions": "Data = 0x0000, TA = 25°C, IOUT1",
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          "name": "Output Leakage Current",
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          "conditions": "Input resistance TC = −50 ppm/°C",
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        {
          "name": "Input Capacitance, Zero-Scale Code",
          "symbol": "",
          "kind": "electrical",
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          "typ": 18,
          "max": 22,
          "conditions": "Zero-scale code",
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        {
          "name": "Input Capacitance, Full-Scale Code",
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          "conditions": "Full-scale code",
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          "kind": "electrical",
          "unit": "V",
          "min": 2,
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          "max": null,
          "conditions": "VDD = 3.6 V to 5 V",
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          "source": "datasheet"
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        {
          "name": "Input High Voltage",
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          "min": 1.7,
          "typ": null,
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          "conditions": "VDD = 2.5 V to 3.6 V",
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          "source": "datasheet"
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          "symbol": "VIL",
          "kind": "electrical",
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          "min": null,
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          "max": 0.8,
          "conditions": "VDD = 2.7 V to 5.5 V",
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          "source": "datasheet"
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        {
          "name": "Input Low Voltage",
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          "conditions": "VDD = 2.5 V to 2.7 V",
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          "source": "datasheet"
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        {
          "name": "Output Low Voltage",
          "symbol": "VOL",
          "kind": "electrical",
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          "max": 0.4,
          "conditions": "VDD = 4.5 V to 5 V, ISINK = 200 µA",
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          "source": "datasheet"
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        {
          "name": "Input Leakage Current",
          "symbol": "IIL",
          "kind": "electrical",
          "unit": "µA",
          "min": -1,
          "typ": null,
          "max": 1,
          "conditions": "TA = 25°C",
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          "source": "datasheet"
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        {
          "name": "Input Leakage Current",
          "symbol": "IIL",
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          "max": 10,
          "conditions": "TA = −40°C to +125°C",
          "source_page": 3,
          "source": "datasheet"
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        {
          "name": "Digital Input Capacitance",
          "symbol": "",
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          "max": 10,
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        {
          "name": "Output Voltage Settling Time to ±1 mV of FS",
          "symbol": "",
          "kind": "timing",
          "unit": "ns",
          "min": null,
          "typ": 100,
          "max": 110,
          "conditions": "VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s",
          "source_page": 3,
          "source": "datasheet"
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        {
          "name": "Output Voltage Settling Time to ±4 mV of FS",
          "symbol": "",
          "kind": "timing",
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          "min": null,
          "typ": 24,
          "max": 40,
          "conditions": "VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s",
          "source_page": 3,
          "source": "datasheet"
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        {
          "name": "Output Voltage Settling Time to ±16 mV of FS",
          "symbol": "",
          "kind": "timing",
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          "min": null,
          "typ": 16,
          "max": 33,
          "conditions": "VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s",
          "source_page": 3,
          "source": "datasheet"
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          "name": "Digital Delay",
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          "typ": 20,
          "max": 40,
          "conditions": "Interface delay time",
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          "source": "datasheet"
        },
        {
          "name": "10%-to-90% Settling Time",
          "symbol": "",
          "kind": "timing",
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          "min": null,
          "typ": 10,
          "max": 30,
          "conditions": "Rise and fall time, VREF = 10 V, RLOAD = 100 Ω",
          "source_page": 4,
          "source": "datasheet"
        },
        {
          "name": "Reference Multiplying Bandwidth",
          "symbol": "",
          "kind": "electrical",
          "unit": "MHz",
          "min": null,
          "typ": 12,
          "max": null,
          "conditions": "VREF = ±3.5 V, DAC loaded with all 1s",
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          "source": "datasheet"
        },
        {
          "name": "Power Supply Range",
          "symbol": "VDD",
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          "min": 2.5,
          "typ": null,
          "max": 5.5,
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        },
        {
          "name": "Supply Current",
          "symbol": "IDD",
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          "unit": "µA",
          "min": null,
          "typ": 0.4,
          "max": 10,
          "conditions": "TA = −40°C to +125°C, logic inputs = 0 V or VDD",
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        {
          "name": "Supply Current",
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          "max": 0.6,
          "conditions": "TA = 25°C, logic inputs = 0 V or VDD",
          "source_page": 4,
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        {
          "name": "Maximum clock frequency",
          "symbol": "fSCLK",
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          "conditions": "VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V",
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        {
          "name": "SCLK cycle time",
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          "conditions": "VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V",
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        {
          "name": "SCLK high time",
          "symbol": "t2",
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          "min": 8,
          "typ": null,
          "max": null,
          "conditions": "VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V",
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        {
          "name": "SCLK low time",
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        {
          "name": "SYNC falling edge to SCLK active edge setup time",
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          "name": "Data setup time",
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        {
          "name": "Data hold time",
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          "conditions": "VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V",
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        {
          "name": "SYNC rising edge to SCLK active edge setup time",
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          "conditions": "VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V",
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        {
          "name": "Minimum SYNC high time",
          "symbol": "t8",
          "kind": "timing",
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          "conditions": "VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V",
          "source_page": 4,
          "source": "datasheet"
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        {
          "name": "SCLK active edge to SDO valid",
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          "conditions": "VDD = 4.5 V to 5.5 V",
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          "source": "datasheet"
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        {
          "name": "SCLK active edge to SDO valid",
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          "conditions": "VDD = 2.5 V to 5.5 V",
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