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AD5446YRMZ

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Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad5446yrmzfactory-2.0.0extractor-text

Verified AD5446YRMZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5446YRMZ · MSOP-10 · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C461537, digikey 505-AD5446YRMZ-ND, mouser 584-AD5446YRMZ
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-xullfw_t/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5446yrmz.kicad_sym✓ ad5446yrmz.kicad_mod✓ ad5446yrmz.step
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AD5446YRMZ

Analog Devices · Digital To Analog Converters (DACs) · MSOP-10

AD5446YRMZ from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IOUT1 output DAC current output.
2 IOUT2 passive DAC analog ground, which should normally be tied to the analog ground of the system.
3 GND power_in Ground pin.
4 SCLK input Serial clock input; data is clocked into the input shift register on the falling edge by default, or on the rising edge if configured via the serial control bits.
5 SDIN input Serial data input; data is clocked into the 16-bit input register on the active edge of the serial clock, falling edge by default on power-up.
6 SYNC input Active-low frame synchronization input; when taken low data is loaded to the shift register on the active clock edges, and the output updates on the rising edge of SYNC.
7 SDO output Serial data output for daisy-chaining several parts; by default data is clocked out on the rising edge of SCLK, always on the alternate edge to data loaded into the shift register.
8 VDD power_in Positive power supply input, operable from 2.5 V to 5.5 V.
9 VREF power_in DAC reference voltage input, with a ±10 V reference input range.
10 RFB passive DAC feedback resistor that establishes the voltage output by connecting to an external amplifier output.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category Data Converters
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Resolution (AD5446) 14 Bits 3
Relative Accuracy INL -2 2 LSB AD5446 3
Differential Nonlinearity DNL -1 2 LSB AD5446, guaranteed monotonic 3
Total Unadjusted Error TUE -4 4 LSB AD5446 3
Gain Error -2.5 2.5 LSB AD5446 3
Gain Error Temperature Coefficient 2 ppm FSR/°C ±2 typical, guaranteed by design and characterization 3
Output Leakage Current -1 1 nA Data = 0x0000, TA = 25°C, IOUT1 3
Output Leakage Current -10 10 nA Data = 0x0000, TA = −40°C to +125°C, IOUT1 3
Reference Input Range -10 10 V 3
VREF Input Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C 3
RFB Feedback Resistance RFB 7 9 11 kΩ Input resistance TC = −50 ppm/°C 3
Input Capacitance, Zero-Scale Code 18 22 pF Zero-scale code 3
Input Capacitance, Full-Scale Code 18 22 pF Full-scale code 3
Input High Voltage VIH 2 V VDD = 3.6 V to 5 V 3
Input High Voltage VIH 1.7 V VDD = 2.5 V to 3.6 V 3
Input Low Voltage VIL 0.8 V VDD = 2.7 V to 5.5 V 3
Input Low Voltage VIL 0.7 V VDD = 2.5 V to 2.7 V 3
Output Low Voltage VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 µA 3
Input Leakage Current IIL -1 1 µA TA = 25°C 3
Input Leakage Current IIL -10 10 µA TA = −40°C to +125°C 3
Digital Input Capacitance 10 pF 3
Output Voltage Settling Time to ±1 mV of FS 100 110 ns VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s 3
Output Voltage Settling Time to ±4 mV of FS 24 40 ns VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s 3
Output Voltage Settling Time to ±16 mV of FS 16 33 ns VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s 3
Digital Delay 20 40 ns Interface delay time 3
10%-to-90% Settling Time 10 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 4
Reference Multiplying Bandwidth 12 MHz VREF = ±3.5 V, DAC loaded with all 1s 3
Power Supply Range VDD 2.5 5.5 V 4
Supply Current IDD 0.4 10 µA TA = −40°C to +125°C, logic inputs = 0 V or VDD 4
Supply Current IDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD 4
Maximum clock frequency fSCLK 50 MHz VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
SCLK cycle time t1 20 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
SCLK high time t2 8 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
SCLK low time t3 8 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
SYNC falling edge to SCLK active edge setup time t4 8 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
Data setup time t5 5 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
Data hold time t6 4.5 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
SYNC rising edge to SCLK active edge setup time t7 5 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
Minimum SYNC high time t8 30 ns VDD = 4.5 V to 5.5 V and 2.5 V to 5.5 V 4
SCLK active edge to SDO valid t9 23 ns VDD = 4.5 V to 5.5 V 4
SCLK active edge to SDO valid t9 30 ns VDD = 2.5 V to 5.5 V 4
Update Rate 2.7 MSPS Consists of cycle time, SYNC high time, data setup time and output voltage settling time 4
VDD to GND VDD -0.3 7 V TA = 25°C 6
VREF, RFB to GND -12 12 V TA = 25°C 6
IOUT1, IOUT2 to GND -0.3 7 V TA = 25°C 6
Logic Inputs and Outputs -0.3 V Upper limit printed as VDD + 0.3 V 6
Input Current (All Pins Except Supplies) -10 10 mA TA = 25°C 6
Operating Temperature Range -40 125 °C Extended (Y Version) 6
Storage Temperature Range -65 150 °C 6
Junction Temperature 150 °C 6
Thermal Impedance, 10-lead MSOP θJA 206 °C/W 10-lead MSOP 6
Lead Temperature, Soldering 300 °C 10 sec 6
IR Reflow, Peak Temperature 235 °C <20 sec 6

CAD (KiCad official)

  • Symbol: AD5446YRMZ
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5446yrmz-etched.step / ad5446yrmz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5446yrmz.step / ad5446yrmz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (25 pp, sha256 df4ce99d21387139, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF