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AD5443YRMZ

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Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5443yrmzfactory-2.0.0extractor-text

Verified AD5443YRMZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5443YRMZ · MSOP-10 · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C578201, digikey AD5443YRMZ-ND, mouser 584-AD5443YRMZ
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-i4ab_j64/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.24)
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5443yrmz.kicad_sym✓ ad5443yrmz.kicad_mod✓ ad5443yrmz.step
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AD5443YRMZ

Analog Devices · Digital To Analog Converters (DACs) · MSOP-10

AD5443YRMZ from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IOUT1 output DAC current output terminal of the R-2R DAC, which feeds the external current-to-voltage precision amplifier.
2 IOUT2 power_in DAC analog ground, which should normally be tied to the analog ground of the system.
3 GND power_in Digital ground pin for the device.
4 SCLK input Serial clock input that clocks data in on the falling edge by default (rising edge selectable by control bits) and accommodates clock rates up to 50 MHz.
5 SDIN input Serial data input that is clocked into the 16-bit input register on the active SCLK edge, falling edge by default and changeable to rising edge by control bits.
6 SYNC input Active-low frame synchronization input that, when taken low, powers on the SCLK and DIN buffers, enables the input shift register, and latches data on the 16th active clock edge.
7 SDO output Serial data output used for daisy-chaining and for DAC register readback, operating with a VDD of 3.0 V to 5.5 V.
8 VDD power_in Positive power supply input that can be operated from 2.5 V to 5.5 V.
9 VREF power_in DAC reference voltage input that sets the full-scale output current; the datasheet specifies a reference input range of ±10 V (stated on page 3).
10 RFB passive DAC feedback resistor pin, connected to the external amplifier output to establish the DAC voltage output.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy -1 1 LSB 3
Differential Nonlinearity -1 2 LSB Guaranteed monotonic 3
Gain Error -10 10 mV 3
Gain Error Temperature Coefficient -5 5 ppm FSR/°C 3
Output Leakage Current -10 10 nA Data = 0x0000, TA = 25°C, IOUT1 3
Output Leakage Current -20 20 nA Data = 0x0000, T = −40°C to 125°C, IOUT1 3
Reference Input Range -10 10 V 3
VREF Input Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C 3
RFB Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C 3
Input Capacitance (Code Zero Scale) 3 6 pF Code Zero Scale 3
Input Capacitance (Code Full Scale) 5 8 pF Code Full Scale 3
Input High Voltage VIH 1.7 V 3
Input Low Voltage VIL 0.6 V 3
Output Low Voltage VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA 3
Input Leakage Current IIL 1 μA 3
Digital Input Capacitance 4 10 pF 3
Output Capacitance (IOUT1) 12 17 pF All 0s loaded 4
Output Capacitance (IOUT1) 10 12 pF All 1s loaded 4
Output Capacitance (IOUT2) 22 25 pF All 0s loaded 4
Output Capacitance (IOUT2) 10 12 pF All 1s loaded 4
Output Voltage Settling Time 50 100 ns Measured to ±16 mV of FS 3
Output Voltage Settling Time 55 110 ns Measured to ±4 mV of FS 3
Output Voltage Settling Time 90 160 ns Measured to ±1 mV of FS 3
Digital Delay 40 75 ns Interface delay time 3
10% to 90% Rise/Fall Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 3
Power Supply Range 2.5 5.5 V 4
IDD (Power Supply Current) IDD 0.4 5 µA T = −40°C to +125°C, logic inputs = 0 V or VDD 4
fSCLK (Max Clock Frequency) fSCLK 50 MHz Max clock frequency 5
SCLK cycle time t1 20 ns VDD = 2.5 V to 5.5 V 5
SCLK high time t2 8 ns VDD = 2.5 V to 5.5 V 5
SCLK low time t3 8 ns VDD = 2.5 V to 5.5 V 5
SYNC falling edge to SCLK active edge setup time t4 13 ns VDD = 2.5 V to 5.5 V 5
Data setup time t5 5 ns VDD = 2.5 V to 5.5 V 5
Data hold time t6 3 ns VDD = 2.5 V to 5.5 V 5
SYNC rising edge to SCLK active edge t7 5 ns VDD = 2.5 V to 5.5 V 5
Minimum SYNC high time t8 30 ns VDD = 2.5 V to 5.5 V 5
SCLK active edge to SDO valid t9 80 120 ns VDD = 2.5 V to 5.5 V 5
SCLK active edge to SDO valid t9 45 65 ns VDD = 4.5 V to 5.5 V 5
Operating Temperature Range (Extended Industrial, Y Version) -40 125 °C 6
VDD to GND -0.3 7 V 6
VREF, RFB to GND -12 12 V 6
Storage Temperature Range -65 150 °C 6
Junction Temperature 150 °C 6
Lead Temperature, Soldering (10 sec) 300 °C 10 sec 6
IR Reflow, Peak Temperature 235 °C <20 sec 6
IDD (Power Supply Current) IDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD 4
Power Supply Sensitivity 0.001 %/% ΔVDD = ±5% 4
θJA Thermal Impedance (10-lead MSOP) θJA 206 °C/W 6

CAD (KiCad official)

  • Symbol: AD5443YRMZ
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5443yrmz-etched.step / ad5443yrmz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5443yrmz.step / ad5443yrmz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 3a5853dd23b7baf4, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF