AD5441BRMZ from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VREF	power_in	DAC reference input pin that establishes the DAC full-scale voltage, with constant input resistance vs. code (absolute maximum ±18 V to GND).
2	RFB	passive	Internal matching feedback resistor, connected to the external op amp output (absolute maximum ±18 V to GND).
3	IOUT	output	DAC current output, with full-scale output 1 LSB less than the reference input voltage -VREF.
4	GND	power_in	Analog and digital ground.
5	LD	input	Level-sensitive active-low load strobe that transfers shift-register data to the DAC register while active low.
6	SRI	input	12-bit serial register input where data loads directly into the shift register MSB first and extra leading bits are ignored.
7	CLK	input	Clock input where the positive edge clocks data into the shift register.
8	VDD	power_in	Positive power supply input with a specified range of operation of 5 V ± 10%.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-8
Category	ADC/DAC/Data Conversion
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy	INL	-0.5		0.5	LSB		3
Differential Nonlinearity	DNL	-0.5		0.5	LSB	All grades monotonic to 12 bits	3
Gain Error	GFSE	-1		1	LSB	Data = FFFH	3
Gain Temperature Coefficient	TCGFS	-5		5	ppm/°C	IOUT pin measured	3
Output Leakage Current	ILKG	-5		5	nA	Data = 000H, IOUT pin measured	3
Output Leakage Current	ILKG	-25		25	nA	TA = -40°C, +125°C, data = 000H, IOUT pin measured	3
Zero-Scale Error	IZSE	-0.03		0.03	LSB	Data = 000H	3
Zero-Scale Error	IZSE	-0.15		0.15	LSB	TA = −40°C, +125°C, data = 000H	3
Input Resistance	RREF	7		15	kΩ	Absolute temperature coefficient < 50 ppm/°C	3
Power Supply Range	VDD RANGE	2.5		5.5	V		3
Power Dissipation	PDISS	2.5		5.5	μW	VLOGIC = 0 V or VDD	3
Tdata setup	tDS	10			ns	2.5 V supply column; data setup	4
Tdata setup	tDS	5			ns	5.5 V supply column; data setup	4
Data hold	tDH	5			ns	2.5 V supply column; data hold	4
Clock width high	tCH	15			ns	2.5 V supply column	4
Clock width high	tCH	10			ns	5.5 V supply column	4
Clock width low	tCL	15			ns	2.5 V supply column	4
Clock width low	tCL	10			ns	5.5 V supply column	4
Load pulse width	tLD	20			ns	2.5 V supply column	4
Load pulse width	tLD	10			ns	5.5 V supply column	4
LD DAC high to MSB CLK high	tLD1	0			ns	2.5 V supply column	4
LSB CLK to LD DAC	tASB	0			ns	2.5 V supply column	4
VDD to GND	VDD	-0.3		8	V		5
VREF to GND	VREF	-18		18	V		5
RFB to GND	RFB	-18		18	V		5
Logic Inputs to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	5
IOUT to GND	IOUT	-0.3			V	Upper limit printed as VDD + 0.3 V	5
IOUT Short Circuit to GND				50	mA		5
Maximum Junction Temperature	TJ max			150	°C		5
Operating Temperature Range		-40		125	°C		5
Storage Temperature Range		-65		150	°C		5
Lead Temperature (Soldering)				300	°C	10 sec	5
Input Capacitance	CREF		5		pF		3
Output Capacitance	COUT		1		pF	Data = 000H	3
Output Capacitance	COUT		4		pF	Data = FFFH	3
Digital Input Low	VIL		0.8		V		3
Digital Input High	VIH		2.4		V		3
Input Leakage Current	IIL		1		μA	VLOGIC = 0 V to 5 V	3
Input Capacitance	CIL		4		pF	VLOGIC = 0 V	3
Output Current Settling Time	tS		5		μs	To ±0.01% of full-scale, external op amp OP42	3
Output Current Settling Time	tS		0.5		μs	To ±0.01% of full-scale, 100 Ω terminated to ground	3
DAC Glitch	Q		40		nVs	Data = 000H to FFFH to 000H, VREF = 0 V, OP42	3
DAC Glitch	Q		1		nVs	Data = 000H to FFFH to 000H, VREF = 0 V, 100 Ω	3
Digital Feedthrough			5		nV	Using external op amp OP42	3
Feedthrough (VOUT/VREF)	FT		1.4		mV p-p	VREF = 20 V p-p, data = 000H, f = 10 kHz	3
Total Harmonic Distortion	THD		-85		dB	VREF = 6 V rms, data = FFFH, f = 1 kHz	3
Output Noise Density	en		17		nV/√Hz	10 Hz to 100 kHz between RFB and IOUT	3
Multiplying Bandwidth	BW		1.9		MHz	−3 dB, VOUT/VREF, VREF = 100 mV rms, data = FFFH	3
Positive Supply Current	IDD		10		μA	VLOGIC = 0 V or VDD	3
Power Supply Sensitivity	PSS		0.002		%/%	ΔVDD = ±5%	3
Thermal Resistance, junction-to-ambient (8-Lead MSOP)	θJA		142		°C/W	Worst case, surface-mount device soldered in circuit board	5
Thermal Resistance, junction-to-case (8-Lead MSOP)	θJC		44		°C/W	Worst case, surface-mount device soldered in circuit board	5

CAD (KiCad official)

Symbol: AD5441BRMZ
Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
3D model: MSOP-8 (KiCad packages3D, STEP)
3D model files: ad5441brmz-etched.step / ad5441brmz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5441brmz.step / ad5441brmz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (16 pp, sha256 e59114a066cad0c1, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5441BRMZ

Verified AD5441BRMZ

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3D Model

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