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AD5432YRMZ

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Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD5432YRMZ

Analog Devices · Digital To Analog Converters (DACs) · MSOP-10

AD5432YRMZ from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IOUT1 output DAC current output; the output current is set by VREF and the DAC code, and it should be tied to the amplifier input in the external current-to-voltage circuit.
2 IOUT2 power_in DAC analog ground, which should normally be tied to the analog ground of the system.
3 GND power_in Digital ground pin.
4 SCLK input Serial clock input that accepts clock rates up to 50 MHz; data is clocked in on the falling edge by default and can be set to the rising edge through the control bits.
5 SDIN input Serial data input that is clocked into the 16-bit input register on the active SCLK edge, falling edge by default.
6 SYNC input Active-low frame synchronization input that enables the SCLK and DIN buffers and the input shift register, and latches data on the 16th active clock edge.
7 SDO output Serial data output used for daisy-chaining and register readback; it operates with VDD of 3.0 V to 5.5 V.
8 VDD power_in Positive power supply input that can be operated from 2.5 V to 5.5 V.
9 VREF power_in DAC reference voltage input with a reference input range of ±10 V, which sets the full-scale output current.
10 RFB passive DAC feedback resistor pin, connected to the external amplifier output to establish the DAC voltage output.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Range VDD 2.5 5.5 V 3
Reference Input Range VREF -10 10 V 3
Relative Accuracy -0.5 0.5 LSB AD5432 (10-bit) 3
Differential Nonlinearity -1 1 LSB AD5432 (10-bit); Guaranteed monotonic 3
Gain Error -10 10 mV 3
Gain Error Temperature Coefficient -5 5 ppm FSR/°C 3
Output Leakage Current IOUT1 -10 10 nA Data = 0x0000, TA = 25°C, IOUT1 3
Output Leakage Current IOUT1 -20 20 nA Data = 0x0000, T = −40°C to 125°C, IOUT1 3
VREF Input Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C 3
RFB Resistance RFB 8 10 12 kΩ Input resistance TC = −50 ppm/°C 3
Input High Voltage VIH 1.7 V 3
Input Low Voltage VIL 0.6 V 3
Output Low Voltage VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 μA 3
Input Leakage Current IIL 1 μA 3
Input Capacitance 4 10 pF 3
Power Supply Sensitivity 0.001 %/% ΔVDD = ±5% 4
IDD IDD 0.6 μA TA = 25°C, logic inputs = 0 V or VDD 4
IDD IDD 0.4 5 μA T = −40°C to +125°C, logic inputs = 0 V or VDD 4
Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V; DAC loaded all 1s 3
Output Voltage Settling Time, measured to ±16 mV of FS 50 100 ns VREF = 10 V; RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s 3
Output Voltage Settling Time, measured to ±4 mV of FS 55 110 ns VREF = 10 V; RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s 3
Output Voltage Settling Time, measured to ±1 mV of FS 90 160 ns VREF = 10 V; RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s 3
Digital Delay 40 75 ns Interface delay time 3
10% to 90% Rise/Fall Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 3
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, VREF = 0 V 3
Max Clock Frequency fSCLK 50 MHz Max clock frequency 5
SCLK Cycle Time t1 20 ns SCLK cycle time 5
SCLK High Time t2 8 ns SCLK high time 5
SCLK Low Time t3 8 ns SCLK low time 5
SYNC Falling Edge to SCLK Active Edge Setup Time t4 13 ns SYNC falling edge to SCLK active edge setup time 5
Data Setup Time t5 5 ns Data setup time 5
Data Hold Time t6 3 ns Data hold time 5
SYNC Rising Edge to SCLK Active Edge t7 5 ns SYNC rising edge to SCLK active edge 5
Minimum SYNC High Time t8 30 ns Minimum SYNC high time 5
SCLK Active Edge to SDO Valid t9 80 120 ns VDD 2.5 V to 5.5 V; SCLK active edge to SDO valid 5
SCLK Active Edge to SDO Valid t9 45 65 ns VDD 4.5 V to 5.5 V; SCLK active edge to SDO valid 5
VDD to GND VDD -0.3 7 V TA = 25°C, unless otherwise noted 6
VREF, RFB to GND VREF, RFB -12 12 V TA = 25°C, unless otherwise noted 6
Operating Temperature Range, Extended Industrial (Y Version) TA -40 125 °C Y version 6
Storage Temperature Range -65 150 °C 6
Junction Temperature 150 °C 6
Lead Temperature, Soldering 300 °C 10 sec 6
IR Reflow, Peak Temperature 235 °C <20 sec 6
Thermal Impedance θJA θJA 206 °C/W 10-lead MSOP 6

CAD (KiCad official)

  • Symbol: AD5432YRMZ
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5432yrmz-etched.step / ad5432yrmz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5432yrmz.step / ad5432yrmz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 3a5853dd23b7baf4, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF