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AD5424YRUZ-REEL7

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Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified AD5424YRUZ-REEL7

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5424YRUZ-REEL7 · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 28-page datasheet
  • ✓distributor: lcsc C495324, digikey AD5424YRUZ-REEL7TR-ND, mouser 584-AD5424YRUZ-R7
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-pp6invp4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.25)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5424yruz-reel7.kicad_sym✓ ad5424yruz-reel7.kicad_mod✓ ad5424yruz-reel7.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers ad5424yruz-reel7: viewers · Ray 4d ago
ad5424yruz-reel7-etched.glb Publish 0.1.0 · Ray 4d ago
ad5424yruz-reel7-etched.step ad5424yruz-reel7: factory component page (tier=mfr) · Ray 4d ago
ad5424yruz-reel7-hero.glb ad5424yruz-reel7: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
ad5424yruz-reel7-hero.overlay.json Publish 0.1.0 · Ray 4d ago
ad5424yruz-reel7.glb Publish 0.1.0 · Ray 4d ago
ad5424yruz-reel7.kicad_mod Publish 0.1.0 · Ray 4d ago
ad5424yruz-reel7.kicad_sym Publish 0.1.0 · Ray 4d ago
ad5424yruz-reel7.lbr Publish 0.1.0 · Ray 4d ago
ad5424yruz-reel7.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 4d ago

AD5424YRUZ-REEL7

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-16

AD5424YRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IOUT1 output DAC current output.
2 IOUT2 passive DAC analog ground, which must normally be tied to the analog ground of the system.
3 GND power_in Ground.
4 DB7 bidirectional Parallel data bit 7 (MSB), written to the input latch and read back from the DAC register.
5 DB6 bidirectional Parallel data bit 6, written to the input latch and read back from the DAC register.
6 DB5 bidirectional Parallel data bit 5, written to the input latch and read back from the DAC register.
7 DB4 bidirectional Parallel data bit 4, written to the input latch and read back from the DAC register.
8 DB3 bidirectional Parallel data bit 3, written to the input latch and read back from the DAC register.
9 DB2 bidirectional Parallel data bit 2, written to the input latch and read back from the DAC register.
10 DB1 bidirectional Parallel data bit 1, written to the input latch and read back from the DAC register.
11 DB0 bidirectional Parallel data bit 0 (LSB), written to the input latch and read back from the DAC register.
12 CS input Active-low chip select used with R/W to load parallel data to the input latch or read data from the DAC register; the rising edge of CS loads data.
13 R/W input Read/Write: when low, used with CS to load parallel data; when high, used with CS to read back the contents of the DAC register.
14 VDD power_in Positive power supply input, operable from 2.5 V to 5.5 V.
15 VREF power_in DAC reference voltage input terminal (reference input range ±10 V).
16 RFB passive DAC feedback resistor pin, connected to the external amplifier output to establish voltage output for the DAC.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Data Converters
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy INL -0.25 0.25 LSB AD5424 3
Differential Nonlinearity DNL -0.5 0.5 LSB AD5424, Guaranteed monotonic 3
Gain Error -10 10 mV 3
Output Leakage Current -10 10 nA Data = 0×0000, TA = 25°C, IOUT1 3
Output Leakage Current -20 20 nA Data = 0×0000, T = −40°C to +125°C, IOUT1 3
Reference Input Range -10 10 V 3
VREF Input Resistance 8 10 12 kΩ Input resistance TC = -50 ppm/°C 3
RFB Resistance RFB 8 10 12 kΩ Input resistance TC = -50 ppm/°C 3
Input Capacitance, Code Zero Scale 3 6 pF Code Zero Scale 3
Input Capacitance, Code Full Scale 5 8 pF Code Full Scale 3
Input High Voltage VIH 1.7 V 3
Input Low Voltage VIL 0.6 V 3
Output Low Voltage VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 µA 3
Input Leakage Current IIL 1 µA 3
Digital Input Capacitance 4 10 pF 3
Output Voltage Settling Time 30 60 ns Measured to ±16 mV of full scale, VREF = ±3.5 V, RLOAD = 100 Ω 3
Output Voltage Settling Time 35 70 ns Measured to ±4 mV of full scale, VREF = ±3.5 V, RLOAD = 100 Ω 3
Output Voltage Settling Time 80 120 ns Measured to ±1 mV of full scale, VREF = ±3.5 V, RLOAD = 100 Ω 3
Digital Delay 20 40 ns Interface delay time 3
10% to 90% Settling Time 15 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω 3
Output Capacitance IOUT1 12 17 pF All 0s loaded 4
Output Capacitance IOUT1 25 30 pF All 1s loaded 4
Output Capacitance IOUT2 22 25 pF All 0s loaded 4
Output Capacitance IOUT2 10 12 pF All 1s loaded 4
Power Supply Range VDD 2.5 5.5 V 4
Supply Current IDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD 4
Supply Current IDD 0.4 5 µA Logic inputs = 0 V or VDD, T= −40°C to +125°C 4
R/W to CS setup time t1 0 ns VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V 5
R/W to CS hold time t2 0 ns VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V 5
CS low time (write cycle) t3 10 ns VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V 5
Data setup time t4 6 ns VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V 5
Data hold time t5 0 ns VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V 5
R/W high to CS low t6 5 ns VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V 5
CS min high time t7 9 ns VDD = 2.5 V to 5.5 V 5
CS min high time t7 7 ns VDD = 4.5 V to 5.5 V 5
Data access time t8 20 40 ns VDD = 2.5 V to 5.5 V 5
Data access time t8 10 20 ns VDD = 4.5 V to 5.5 V 5
Bus relinquish time t9 5 10 ns VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V 5
VDD to GND VDD -0.3 7 V TA = 25°C 6
VREF, RFB to GND -12 12 V TA = 25°C 6
IOUT1, IOUT2 to GND -0.3 7 V TA = 25°C 6
Logic Inputs and Output -0.3 V to VDD + 0.3 V max; TA = 25°C 6
Operating Temperature Range (Y Version) -40 125 °C Extended Industrial 6
Storage Temperature Range -65 150 °C 6
Junction Temperature 150 °C 6
Lead Temperature, Soldering (10 sec) 300 °C 6
IR Reflow, Peak Temperature (<20 sec) 235 °C 6
16-Lead TSSOP Thermal Impedance θJA 150 °C/W 16-Lead TSSOP 6
Gain Error Temperature Coefficient 5 ppm FSR/°C ±5 as printed; guaranteed by design 3
Power Supply Sensitivity 0.001 %/% ΔVDD = ±5% 4
Reference Multiplying Bandwidth 10 MHz VREF = ±3.5 V; DAC loaded all 1s 3

CAD (KiCad official)

  • Symbol: AD5424YRUZ-REEL7
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad5424yruz-reel7-etched.step / ad5424yruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5424yruz-reel7.step / ad5424yruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 8e6ae7a875ffd586, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF