component
AD5422BREZ-REEL
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DAC), HTSSOP-24. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
ad5422brez-reel: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
d96850b
1mo ago
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336
{
"schema_version": 1,
"type": "component",
"slug": "ad5422brez-reel",
"title": "AD5422BREZ-REEL",
"brief": "Analog Devices Digital To Analog Converters (DAC), HTSSOP-24. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"data acquisition",
"ad5422brez-reel"
],
"component": {
"mpn": "AD5422BREZ-REEL",
"manufacturer": "Analog Devices",
"package": "HTSSOP-24",
"pin_count": 25,
"category": "Data Acquisition",
"subcategory": "Digital To Analog Converters (DAC)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881959850688512",
"parts": {
"symbol": "ad5422brez-reel.kicad_sym",
"footprint": "ad5422brez-reel.kicad_mod",
"model_3d": "ad5422brez-reel-etched.glb",
"model_3d_plain": "ad5422brez-reel.glb",
"model_3d_step": "ad5422brez-reel-etched.step",
"model_3d_step_plain": "ad5422brez-reel.step",
"lbr": "ad5422brez-reel.lbr"
},
"distributor_links": {},
"pins": [
{
"number": "1",
"name": "AVSS",
"type": "power_in",
"description": "Negative analog supply. Range −3 V to −24 V. May be tied to 0 V when only a unipolar output range is used."
},
{
"number": "2",
"name": "DVCC",
"type": "power_in",
"description": "Digital supply. Range 2.7 V to 5.5 V. Leave floating if the internal 4.5 V LDO is used (DVCC SELECT tied to GND) so this pin can be driven by the internal LDO output."
},
{
"number": "3",
"name": "FAULT",
"type": "output",
"description": "Fault alert, active-low, open-drain output. Asserted when an open circuit is detected in current mode or when an over-temperature condition is detected. Requires an external pull-up."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Ground reference pin (0 V)."
},
{
"number": "5",
"name": "CLEAR SELECT",
"type": "input",
"description": "Selects the voltage-output clear code loaded on a CLEAR event: zero scale or mid-scale (see Table 21)."
},
{
"number": "6",
"name": "CLEAR",
"type": "input",
"description": "Active-high asynchronous clear input. Assertion drives the current output to the low end of the selected range and the voltage output to the user-selected value (zero or mid-scale)."
},
{
"number": "7",
"name": "LATCH",
"type": "input",
"description": "Positive-edge sensitive latch. On the rising edge, the contents of the input shift register are transferred into the DAC register and the output updates."
},
{
"number": "8",
"name": "SCLK",
"type": "input",
"description": "Serial clock input. Data is shifted into the input register on the rising edge of SCLK. Maximum clock rate 30 MHz."
},
{
"number": "9",
"name": "SDIN",
"type": "input",
"description": "Serial data input. Data must be valid on the rising edge of SCLK."
},
{
"number": "10",
"name": "SDO",
"type": "output",
"description": "Serial data output. Used to daisy-chain multiple devices or to read back the shift register contents. Data is clocked out on the rising edge of SCLK (see Figure 3, Figure 4)."
},
{
"number": "11",
"name": "GND",
"type": "power_in",
"description": "Ground reference pin (0 V)."
},
{
"number": "12",
"name": "GND",
"type": "power_in",
"description": "Ground reference pin (0 V)."
},
{
"number": "13",
"name": "RSET",
"type": "passive",
"description": "Optional external precision, low-drift 15 kΩ current-set resistor connection. Using an external RSET improves the IOUT temperature drift performance."
},
{
"number": "14",
"name": "REFOUT",
"type": "output",
"description": "On-chip 5 V ± 2 mV precision reference output."
},
{
"number": "15",
"name": "REFIN",
"type": "input",
"description": "External reference voltage input. Input range 4 V to 5 V; use REFIN = 5 V to achieve rated performance."
},
{
"number": "16",
"name": "DVCC SELECT",
"type": "input",
"description": "When tied to GND, the internal supply is disabled and an external supply must be connected to DVCC. Leave unconnected to enable the internal 4.5 V LDO on DVCC."
},
{
"number": "17",
"name": "CCOMP",
"type": "passive",
"description": "Optional voltage-output compensation capacitor connection. Connecting a 4 nF cap between CCOMP and VOUT allows driving up to 1 µF capacitive loads at the expense of output amplifier bandwidth and settling time."
},
{
"number": "18",
"name": "NC",
"type": "unconnected",
"description": "No connect. Do not connect to this pin."
},
{
"number": "19",
"name": "IOUT",
"type": "output",
"description": "Current output pin. Programmable 4-20 mA, 0-20 mA or 0-24 mA current-loop output."
},
{
"number": "20",
"name": "BOOST",
"type": "output",
"description": "Optional external boost transistor connection. Connecting an external pass transistor reduces power dissipation in the AD5412/AD5422."
},
{
"number": "21",
"name": "VOUT",
"type": "output",
"description": "Buffered analog voltage output. The output amplifier can drive a 1 kΩ / 2000 pF load directly."
},
{
"number": "22",
"name": "+VSENSE",
"type": "input",
"description": "Positive load-sense (Kelvin) connection for the voltage output."
},
{
"number": "23",
"name": "-VSENSE",
"type": "input",
"description": "Negative load-sense (Kelvin) connection for the voltage output."
},
{
"number": "24",
"name": "AVDD",
"type": "power_in",
"description": "Positive analog supply. Range 10.8 V to 60 V."
},
{
"number": "25",
"name": "EPAD",
"type": "passive",
"description": "Exposed thermal pad. May be tied to 0 V for unipolar output ranges, or left electrically unconnected when a supply connection is already made at AVSS. Thermally connect to a copper plane for improved heat dissipation."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881959850688512",
"pages": 44,
"sha256": "9872399914887477",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 25,
"described": 25,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad5422brez-reel.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.72,
7.8,
1.6
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "6526f32bf2be6ab3eec46705f8c6c88534ee1677ebeaf32903f98f1aa68a9e0c",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad5422brez-reel-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.72,
7.8,
1.6
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "13b549783995ca32f053c892f6e198bda3409825f3829b84fc8751e2dce09490",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Analog Devices",
"Package": "HTSSOP-24",
"Category": "Data Acquisition",
"Pins": "25"
}
},
"variants": [
{
"mpn": "AD5422BREZ-REEL",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REEL7",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELAREZ",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELAREZ-REEL",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELAREZ-REEL7",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELBCPZ",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELBCPZ-REEL",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELBCPZ-REEL7",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELACPZ",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELACPZ-REEL",
"kind": "packaging"
},
{
"mpn": "AD5422BREZ-REELACPZ-REEL7",
"kind": "packaging"
}
],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"ad5422brez-reel"
],
"discovery_pitch": "AD5422BREZ-REEL (Analog Devices) component page with datasheet-verified CAD.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ad5422brez-reel.kicad_sym",
"ad5422brez-reel.kicad_mod",
"ad5422brez-reel.glb",
"ad5422brez-reel.step",
"ad5422brez-reel.lbr",
"docs/hero.png",
"docs/ad5422brez-reel-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"visibility": {
"public": true
},
"updated_at": "2026-09-24T15:34:50.994Z"
}