component
AD5422BCPZ-REEL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), LFCSP-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAD5422BCPZ-REEL7
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-40(6x6)
AD5422BCPZ-REEL7 from Analog Devices, in a LFCSP-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection; do not connect to this pin. |
| 2 | FAULT | output | Fault alert open-drain output is asserted low when an open circuit is detected in current mode or an overtemperature is detected, and must be connected to a pull-up resistor. |
| 3 | GND | power_in | This pin must be connected to 0 V. |
| 4 | CLEAR SELECT | input | Selects the voltage output clear value, either zero-scale or midscale code (see Table 22). |
| 5 | CLEAR | input | Active-high input that sets the current output to the bottom of the selected range or sets the voltage output to the user-selected value (zero-scale or midscale). |
| 6 | LATCH | input | Positive-edge-sensitive latch; a rising LATCH edge parallel loads the input shift register data into the DAC register and updates the output. |
| 7 | SCLK | input | Serial clock input; data is clocked into the shift register on the rising edge of SCLK, at clock speeds of up to 30 MHz. |
| 8 | SDIN | input | Serial data input; data must be valid on the rising edge of SCLK. |
| 9 | SDO | output | Serial data output used to clock data from the serial register in daisy-chain or readback mode; data is valid on the rising edge of SCLK. |
| 10 | NC | unconnected | No connection; do not connect to this pin. |
| 11 | NC | unconnected | No connection; do not connect to this pin. |
| 12 | GND | power_in | Ground reference pin; must be connected to 0 V. |
| 13 | GND | power_in | Ground reference pin; must be connected to 0 V. |
| 14 | AVSS | power_in | Negative analog supply pin; voltage ranges from -3 V to -24 V and can be connected to 0 V if the output voltage range is unipolar. |
| 15 | GND | power_in | This pin must be connected to 0 V. |
| 16 | RSET | passive | An external precision, low-drift 15 kΩ current setting resistor can be connected to this pin to improve IOUT temperature drift performance. |
| 17 | REFOUT | power_out | Internal reference voltage output; REFOUT = 5 V ± 5 mV. |
| 18 | REFIN | input | External reference voltage input; reference input range is 4 V to 5 V, with REFIN = 5 V for specified performance. |
| 19 | NC | unconnected | No connection; do not connect to this pin. |
| 20 | NC | unconnected | No connection; do not connect to this pin. |
| 21 | NC | unconnected | No connection; do not connect to this pin. |
| 22 | NC | unconnected | No connection; do not connect to this pin. |
| 23 | DVCC SELECT | input | When connected to GND, disables the internal supply so an external supply must be connected to DVCC; leave unconnected to enable the internal supply, with a 0.1 µF capacitor recommended between DVCC and GND. |
| 24 | CCOMP | passive | Optional compensation capacitor connection for the voltage output buffer; a 4 nF capacitor between CCOMP and VOUT allows the voltage output to drive up to 1 µF, at the cost of reduced amplifier bandwidth and increased settling time. |
| 25 | NC | unconnected | No connection; do not connect to this pin. |
| 26 | IOUT | output | Current output pin. |
| 27 | BOOST | passive | Optional external transistor connection that reduces the power dissipated in the AD5412/AD5422 when an external transistor is connected. |
| 28 | CAP1 | passive | Connection for optional output filtering capacitor. |
| 29 | CAP2 | passive | Connection for optional output filtering capacitor; used for HART signal coupling on the LFCSP package. |
| 30 | NC | unconnected | No connection; do not connect to this pin. |
| 31 | NC | unconnected | No connection; do not connect to this pin. |
| 32 | VOUT | output | Buffered analog output voltage; the output amplifier is capable of directly driving a 1 kΩ, 2000 pF load. |
| 33 | +VSENSE | input | Sense connection for the positive voltage output load connection. |
| 34 | −VSENSE | input | Sense connection for the negative voltage output load connection. |
| 35 | NC | unconnected | No connection; do not connect to this pin. |
| 36 | AVDD | power_in | Positive analog supply pin; voltage ranges from 10.8 V to 60 V as printed in Table 7. |
| 37 | AVSS | power_in | Negative analog supply pin; voltage ranges from -3 V to -24 V and can be connected to 0 V if the output voltage range is unipolar. |
| 38 | NC | unconnected | No connection; do not connect to this pin. |
| 39 | DVCC | power_in | Digital supply pin; voltage ranges from 2.7 V to 5.5 V and can also be configured as a 4.5 V LDO output by leaving the DVCC SELECT pin floating. |
| 40 | NC | unconnected | No connection; do not connect to this pin. |
| 41 | EPAD | power_in | Exposed paddle, negative analog supply pin with voltage from -3 V to -24 V; it can be left electrically unconnected if AVSS is supplied, and is recommended to be thermally connected to a copper plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-40(6x6) |
| Category | ADC/DAC/Data Conversion |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVDD to GND | -0.3 | 48 | V | TA = 25°C | 11 | ||
| AVSS to GND | -28 | 0.3 | V | TA = 25°C | 11 | ||
| AVDD to AVSS | -0.3 | 60 | V | TA = 25°C | 11 | ||
| DVCC to GND | DVCC | -0.3 | 7 | V | TA = 25°C | 11 | |
| REFIN/REFOUT to GND | -0.3 | 7 | V | TA = 25°C | 11 | ||
| Operating Temperature Range (Industrial) | TA | -40 | 105 | °C | 11 | ||
| Junction Temperature (TJ max) | TJ | 125 | °C | 11 | |||
| Thermal impedance, 40-lead LFCSP | θJA | 33 | °C/W | JEDEC 2S2P thermal test board with thermal vias | 11 | ||
| AVDD supply range | AVDD | 10.8 | 40 | V | 7 | ||
| AVSS supply range | AVSS | -26.4 | 0 | V | 7 | ||
| /AVSS/ + AVDD | /AVSS/ + AVDD | 10.8 | 52.8 | V | 7 | ||
| DVCC input voltage | DVCC | 2.7 | 5.5 | V | Internal supply disabled | 7 | |
| AIDD, outputs disabled | AIDD | 2.5 | 3 | mA | Outputs unloaded; outputs disabled | 7 | |
| AIDD, current output enabled | AIDD | 3.4 | 4 | mA | Outputs unloaded; current output enabled | 7 | |
| AIDD, voltage output enabled | AIDD | 3.9 | 4.4 | mA | Outputs unloaded; voltage output enabled | 7 | |
| Reference Input Voltage | REFIN | 4.95 | 5 | 5.05 | V | For specified performance | 6 |
| Reference Output Voltage | REFOUT | 4.995 | 5 | 5.005 | V | TA = 25°C | 6 |
| Reference Temperature Coefficient | 1.8 | 10 | ppm/°C | 6 | |||
| DC Input Impedance (REFIN) | 27 | 40 | kΩ | 6 | |||
| Input High Voltage | VIH | 2 | V | JEDEC compliant | 6 | ||
| Input Low Voltage | VIL | 0.8 | V | JEDEC compliant | 6 | ||
| Digital Input Current | -1 | 1 | µA | Per pin | 6 | ||
| SDO Output Low Voltage | VOL | 0.4 | V | Sinking 200 µA | 6 | ||
| FAULT Output Low Voltage | VOL | 0.4 | V | 10 kΩ pull-up resistor to DVCC | 7 | ||
| Total Unadjusted Error (TUE), B version | -0.1 | 0.1 | % FSR | 4 | |||
| Relative Accuracy (INL), AD5422 | -0.008 | 0.008 | % FSR | AD5422 | 4 | ||
| Differential Nonlinearity (DNL) | -1 | 1.3 | LSB | Guaranteed monotonic | 4 | ||
| Bipolar Zero Error | -9 | 9 | mV | Bipolar output range | 4 | ||
| Bipolar Zero Error Temperature Coefficient | -3 | 3 | ppm FSR/°C | Bipolar output range | 4 | ||
| Zero-Scale Error | -8 | 8 | mV | 4 | |||
| Zero-Scale Error TC | -2 | 2 | ppm FSR/°C | 4 | |||
| Offset Error | -6 | 6 | mV | Unipolar output range | 4 | ||
| Offset Error TC | -2 | 2 | ppm FSR/°C | Unipolar output range | 4 | ||
| Gain Error | -0.07 | 0.07 | % FSR | 4 | |||
| Gain Error TC | -3 | 3 | ppm FSR/°C | 4 | |||
| Full-Scale Error | -0.07 | 0.07 | % FSR | 4 | |||
| Full-Scale Error TC | -2 | 2 | ppm FSR/°C | 4 | |||
| VOUT Headroom | 0.5 | 0.8 | V | Output unloaded | 4 | ||
| Total Unadjusted Error (TUE), internal RSET, B version | -0.3 | 0.3 | % FSR | Internal RSET | 5 | ||
| Relative Accuracy (INL), internal RSET, AD5422 | -0.024 | 0.024 | % FSR | AD5422, internal RSET | 5 | ||
| Differential Nonlinearity (DNL), internal RSET | -1 | 1.3 | LSB | Guaranteed monotonic | 5 | ||
| Offset Error, internal RSET | -0.4 | 0.4 | % FSR | Internal RSET | 5 | ||
| Offset Error TC, internal RSET | -28 | 28 | ppm FSR/°C | Internal RSET | 5 | ||
| Gain Error, internal RSET, AD5422 | -0.2 | 0.2 | % FSR | AD5422, internal RSET | 5 | ||
| Gain Error TC, internal RSET | -21 | 21 | ppm FSR/°C | Internal RSET | 5 | ||
| Full-Scale Error, internal RSET | -0.4 | 0.4 | % FSR | Internal RSET | 5 | ||
| Full-Scale Error TC, internal RSET | -13 | 13 | ppm FSR/°C | Internal RSET | 5 | ||
| Current Loop Compliance Voltage | 0 | V | Upper limit printed as AVDD − 2.5 V | 6 | |||
| Output Current Drift vs. Time, internal RSET | 50 | ppm FSR | Drift after 1000 hours, TA = 125°C, internal RSET | 6 | |||
| Resistive Load | 1200 | Ω | 6 | ||||
| Inductive Load | 50 | mH | TA = 25°C | 6 | |||
| Total Unadjusted Error (TUE), external RSET, B version | -0.15 | 0.15 | % FSR | External RSET | 5 | ||
| Relative Accuracy (INL), external RSET, AD5422 | -0.012 | 0.012 | % FSR | AD5422, external RSET | 5 | ||
| Offset Error, external RSET | -0.12 | 0.12 | % FSR | External RSET | 6 | ||
| Offset Error TC, external RSET | -5 | 5 | ppm FSR/°C | External RSET | 6 | ||
| Gain Error, external RSET | -0.15 | 0.15 | % FSR | External RSET | 6 | ||
| Gain Error TC, external RSET | -4 | 4 | ppm FSR/°C | External RSET | 6 | ||
| Full-Scale Error, external RSET | -0.15 | 0.15 | % FSR | External RSET | 6 | ||
| Full-Scale Error TC, external RSET | -9 | 9 | ppm FSR/°C | External RSET | 6 | ||
| Output Current Drift vs. Time, external RSET | 20 | ppm FSR | Drift after 1000 hours, TA = 125°C, external RSET | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | connection is made at the AVSS pin. It is recommended that the paddle be thermally connected to a copper | 13 |
CAD (KiCad official)
- Symbol:
AD5422BCPZ-REEL7 - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: LFCSP-40(6x6) (KiCad packages3D, STEP)
- 3D model files:
ad5422bcpz-reel7-etched.step/ad5422bcpz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5422bcpz-reel7.step/ad5422bcpz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (41 pp, sha256
a8f7ff78526f8fbb, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).