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AD5421BCPZ-REEL7

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Analog Devices Digital To Analog Converters (DAC), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD5421BCPZ-REEL7

Analog Devices · Digital To Analog Converters (DAC) · LFCSP-32(5x5)

AD5421BCPZ-REEL7 from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDIN input Serial data input; data must be valid on the falling edge of SCLK.
2 LDAC input Active-low load DAC input that updates the DAC register and output current; it should not be left unconnected.
3 FAULT output Active-high fault alert output, asserted on loop current out of range, insufficient loop voltage, overtemperature, SPI control loss or communication (PEC) error.
4 COM power_in Ground reference pin for the AD5421; a 4.7 V Zener diode is recommended between LOOP− and COM.
5 DVDD power_out 3.3 V digital power supply output, to be decoupled to COM with 100 nF and 4.7 μF capacitors.
6 ALARM_CURRENT_DIRECTION input Selects upscale alarm current (22.8 mA/24 mA) when connected to DVDD or downscale alarm current (3.2 mA) when connected to COM.
7 RINT/REXT input Connect to DVDD to select the internal current setting resistor or to COM to select the external resistor between REXT1 and REXT2.
8 RANGE0 input Digital input that selects the loop current range together with RANGE1.
9 NC unconnected No connect; do not connect to this pin.
10 RANGE1 input Digital input that selects the loop current range together with RANGE0.
11 COM power_in Ground reference pin for the AD5421; a 4.7 V Zener diode is recommended between LOOP− and COM.
12 COM power_in Ground reference pin for the AD5421; a 4.7 V Zener diode is recommended between LOOP− and COM.
13 REG_SEL2 input Together with REG_SEL0 and REG_SEL1, selects the REGOUT voltage between 1.8 V and 12 V.
14 REG_SEL1 input Together with REG_SEL0 and REG_SEL2, selects the REGOUT voltage between 1.8 V and 12 V.
15 REG_SEL0 input Together with REG_SEL1 and REG_SEL2, selects the REGOUT voltage between 1.8 V and 12 V.
16 NC unconnected No connect; do not connect to this pin.
17 REFIN input Reference voltage input; VREFIN = 2.5 V for specified performance.
18 REFOUT2 power_out Internal 1.22 V reference output; a 100 nF capacitor to COM is recommended.
19 REFOUT1 power_out Internal 2.5 V reference output; a 100 nF capacitor to COM is recommended.
20 CIN passive External capacitor to COM sets the output slew rate control and also serves as the HART FSK input through a capacitor.
21 REXT1 passive Connection for the external current setting resistor; a precision 24 kΩ resistor can be connected between REXT1 and REXT2.
22 REXT2 passive Connection for the external current setting resistor; a precision 24 kΩ resistor can be connected between REXT1 and REXT2.
23 LOOP− passive Loop current return pin, used with COM to sense the loop current across the internal 52 Ω resistor; the voltage at LOOP− is negative with respect to COM.
24 VLOOP input Voltage input with a range of 0 V to 2.5 V, digitized to eight bits for the fault register and intended for loop supply monitoring via a 20:1 divider.
25 NC unconnected No connect; do not connect to this pin.
26 DRIVE output Gate connection for an external depletion mode MOSFET; DRIVE to COM is rated −0.3 V to +11 V.
27 REGIN power_in Voltage regulator input, rated 5.5 V to 52 V with respect to LOOP−, which may be connected directly to the loop voltage or to an external pass transistor.
28 REGOUT power_out Voltage regulator output selectable from 1.8 V to 12 V via REG_SEL0-REG_SEL2, decoupled to COM with a >1 µF capacitor when driving a microconverter supply.
29 IODVDD power_in Digital interface supply; digital thresholds are referenced to it and it accepts 1.71 V to 5.5 V with respect to COM.
30 SDO output Serial data output clocked out on the rising edge of SCLK and valid on the falling edge of SCLK.
31 SCLK input Serial clock input, data clocked in on the falling edge, operating at clock speeds up to 30 MHz.
32 SYNC input Active-low frame synchronization input; data is transferred on SCLK falling edges while low and latched on the rising edge of SYNC.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Data Acquisition
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Regin to COM -0.3 60 V 11
REGOUT to COM -0.3 14 V 11
Digital inputs (RANGE0, RANGE1, RINT/REXT, ALARM_CURRENT_DIRECTION, REG_SEL0-2) to COM -0.3 7 V or DVDD + 0.3 V, whichever is less 11
Digital inputs SCLK, SDIN, SYNC, LDAC to COM -0.3 7 V or IODVDD + 0.3 V, whichever is less 11
Digital outputs SDO, FAULT to COM -0.3 7 V or IODVDD + 0.3 V, whichever is less 11
REFIN to COM -0.3 7 V 11
REFOUT1, REFOUT2 -0.3 4.7 V 11
VLOOP to COM -0.3 60 V 11
LOOP− to COM -5 0.3 V 11
DVDD to COM -0.3 7 V 11
IODVDD to COM -0.3 7 V 11
REXT1, CIN to COM -0.3 4.3 V 11
REXT2 to COM -0.3 0.3 V 11
DRIVE to COM -0.3 11 V 11
Operating temperature range (TA), industrial TA -40 105 °C 11
Storage temperature range -65 150 °C 11
Junction temperature (TJ MAX) TJ MAX 125 °C 11
Thermal resistance junction-to-ambient, 32-lead LFCSP (CP-32-12) θJA 40 °C/W JEDEC 2S2P test board with thermal vias 11
Thermal resistance junction-to-case, 32-lead LFCSP (CP-32-12) θJC 7 °C/W 11
Loop voltage range 5.5 52 V 1
IODVDD digital interface supply IODVDD 1.71 5.5 V 12
Total Unadjusted Error (TUE), internal RSET -0.18 0.18 % FSR B grade 4
Total Unadjusted Error (TUE), internal RSET -0.06 0.011 0.06 % FSR B grade, TA = 25°C 4
Relative Accuracy (INL), internal RSET -0.012 0.006 0.012 % FSR B grade 4
Differential Nonlinearity (DNL) -1 1 LSB Guaranteed monotonic 4
Offset Error -0.056 0.056 % FSR B grade and C grade 4
Offset Error -0.008 0.0008 0.008 % FSR B grade and C grade, TA = 25°C 4
Gain Error -0.107 0.107 % FSR B grade and C grade 4
Gain Error -0.035 0.0058 0.035 % FSR B grade and C grade, TA = 25°C 4
Full-Scale Error -0.126 0.126 % FSR B grade and C grade 4
Full-Scale Error -0.041 0.0065 0.041 % FSR B grade and C grade, TA = 25°C 4
Downscale Alarm Current, internal RSET 3.19 3.21 mA 4
Upscale Alarm Current, internal RSET 22.77 22.83 mA 4 mA to 20 mA and 3.8 mA to 21 mA ranges 4
Upscale Alarm Current, internal RSET 23.97 24.03 mA 3.2 mA to 24 mA range 4
Total Unadjusted Error (TUE), external RSET (24 kΩ) -0.08 0.08 % FSR external RSET (24 kΩ), B grade 4
Total Unadjusted Error (TUE), external RSET (24 kΩ) -0.04 0.003 0.04 % FSR external RSET (24 kΩ), B grade, TA = 25°C 4
Relative Accuracy (INL), external RSET (24 kΩ) -0.012 0.006 0.012 % FSR external RSET (24 kΩ), B grade 4
Offset Error, external RSET (24 kΩ) -0.021 0.021 % FSR external RSET (24 kΩ) 4
Gain Error, external RSET (24 kΩ) -0.03 0.03 % FSR external RSET (24 kΩ) 4
Full-Scale Error, external RSET (24 kΩ) -0.047 0.047 % FSR external RSET (24 kΩ) 5
Downscale Alarm Current, external RSET (24 kΩ) 3.08 3.21 mA external RSET (24 kΩ) 5
Upscale Alarm Current, external RSET (24 kΩ) 22.78 23 mA external RSET (24 kΩ); 4 mA to 20 mA and 3.8 mA to 21 mA ranges 5
Upscale Alarm Current, external RSET (24 kΩ) 23.99 24.01 mA external RSET (24 kΩ); 3.2 mA to 24 mA range 5
Loop Compliance Voltage (LOOP− + value) 5.5 V REGOUT < 5.5 V, loop current = 24 mA 5
Loop Compliance Voltage (LOOP− + value) 12.5 V REGOUT = 12 V, loop current = 24 mA 5
Resistive Load 0 2 kΩ See Figure 21 for a load line graph 5
Power Supply Sensitivity (loop output) 0.1 µA/V Loop current = 12 mA 5
Output TC, internal RSET 3 ppm FSR/°C Loop current = 12 mA, internal RSET 5
REFOUT1 Output Voltage 2.498 2.5 2.503 V TA = 25°C 5
REFOUT1 Temperature Coefficient 2 8 ppm/°C B grade 5
REFOUT2 Output Voltage 1.18 1.227 1.28 V TA = 25°C 5
REGOUT Output Voltage 1.8 12 V See Table 10 6
REGOUT Output Voltage Accuracy -4 2 4 % 6
DVDD Output Voltage 3.17 3.3 3.48 V 6
ADC Accuracy, Die Temperature -5 5 °C 6
ADC Accuracy, VLOOP Input -1 1 % 6
Digital Input Current (SCLK, SYNC, SDIN, LDAC) -0.015 0.015 µA Per pin 6
SDO Output Low Voltage VOL 0.4 V 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts COPPER 1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE SAME POTENTIAL AS THE COM PIN AND TO A COPPER PLANE FOR 12

CAD (KiCad official)

  • Symbol: AD5421BCPZ-REEL7
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad5421bcpz-reel7-etched.step / ad5421bcpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5421bcpz-reel7.step / ad5421bcpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 76646178e298d83d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF