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AD5331BRUZ

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Analog Devices Digital To Analog Converters (DACs), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5331bruzfactory-2.0.0extractor-text

Verified AD5331BRUZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5331BRUZ · TSSOP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 28-page datasheet
  • ✓distributor: lcsc C649599, digikey AD5331BRUZ-ND, mouser 584-AD5331BRUZ
  • ✓family: TSSOP-20_4.4x6.5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-sc6s_0_v/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.24)
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5331bruz.kicad_sym✓ ad5331bruz.kicad_mod✓ ad5331bruz.step
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AD5331BRUZ

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-20

AD5331BRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DB8 input Parallel data input; DB9 is the most significant bit of the parallel data, so DB8 is the bit immediately below it.
2 DB9 input Most significant bit of the parallel data input.
3 VREF power_in Unbuffered reference input for the DAC.
4 VOUT output Output of the DAC, buffered with rail-to-rail operation.
5 GND power_in Ground reference point for all circuitry on the part.
6 CS input Active low chip select input, used in conjunction with WR to write data to the parallel interface.
7 WR input Active low write input, used in conjunction with CS to write data to the parallel interface; data is loaded into the input registers on the rising edge of WR.
8 GAIN input Gain control pin that sets the output range to 0 V to VREF or 0 V to 2 × VREF.
9 CLR input Active low asynchronous control input that clears all input registers and DAC registers to zero.
10 LDAC input Active low control input that updates the DAC registers with the contents of the input registers.
11 PD input Active low power-down pin that puts the DAC into power-down mode.
12 VDD power_in Power supply input operating from 2.5 V to 5.5 V; decouple with 10 μF in parallel with 0.1 μF to GND.
13 DB0 input Parallel data input, one of the eight lower data bits (DB0 to DB7 on pins 13 to 20).
14 DB1 input Parallel data input, one of the eight lower data bits (DB0 to DB7 on pins 13 to 20).
15 DB2 input Parallel data input, one of the eight lower data bits (DB0 to DB7 on pins 13 to 20).
16 DB3 input Parallel data input, one of the eight lower data bits (DB0 to DB7 on pins 13 to 20).
17 DB4 input Parallel data input, one of the eight lower data bits (DB0 to DB7 on pins 13 to 20).
18 DB5 input Parallel data input, one of the eight lower data bits (DB0 to DB7 on pins 13 to 20).
19 DB6 input Parallel data input, one of the eight lower data bits (DB0 to DB7 on pins 13 to 20).
20 DB7 input Parallel data input; DB7 is the most significant of the eight lower data bits (DB0 to DB7 on pins 13 to 20).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20
Category ADC/DAC/Data Conversion
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (AD5331) -4 0.5 4 LSB Linearity tested using reduced code range: Code 28 to Code 1023 3
Differential Nonlinearity (AD5331) -0.5 0.05 0.5 LSB Guaranteed monotonic by design over all codes; linearity tested using reduced code range Code 28 to Code 1023 3
Offset Error -3 0.4 3 % of FSR 3
Gain Error -1 0.15 1 % of FSR 3
Lower Deadband 10 60 mV Lower deadband exists only if offset error is negative 3
Upper Deadband 10 60 mV VDD = 5 V; upper deadband exists only if VREF = VDD 3
Minimum Output Voltage 0.001 V Rail-to-rail operation 3
Input Current -1 1 μA 3
Input Low Voltage VIL 0.8 V VDD = 5 V ± 10% 3
Input Low Voltage VIL 0.6 V VDD = 3 V ± 10% 3
Input Low Voltage VIL 0.5 V VDD = 2.5 V 3
Input High Voltage VIH 2.4 V VDD = 5 V ± 10% 3
Input High Voltage VIH 2.1 V VDD = 3 V ± 10% 3
Input High Voltage VIH 2 V VDD = 2.5 V 3
Supply Voltage VDD 2.5 5.5 V 4
IDD (Normal Mode) IDD 140 250 μA VDD = 4.5 V to 5.5 V; DACs active, excluding load currents; unbuffered reference, VIH = VDD, VIL = GND 4
IDD (Normal Mode) IDD 115 200 μA VDD = 2.5 V to 3.6 V; DACs active, excluding load currents; unbuffered reference, VIH = VDD, VIL = GND 4
IDD (Power-Down Mode) IDD 0.2 1 μA VDD = 4.5 V to 5.5 V 4
IDD (Power-Down Mode) IDD 0.08 1 μA VDD = 2.5 V to 3.6 V 4
Output Voltage Settling Time (AD5331) 7 9 μs VREF = 2 V; ¼ scale to ¾ scale change (0x100 to 0x300) 4
CS to WR setup time t1 0 ns CS to WR setup time 5
CS to WR hold time t2 0 ns CS to WR hold time 5
WR pulse width t3 20 ns WR pulse width 5
Data, GAIN, BUF, HBEN setup time t4 5 ns Data, GAIN, BUF, HBEN setup time 5
Data, GAIN, BUF, HBEN hold time t5 4.5 ns Data, GAIN, BUF, HBEN hold time 5
WR falling to LDAC falling (synchronous mode) t6 5 ns Synchronous mode; WR falling to LDAC falling 5
LDAC falling to WR rising (synchronous mode) t7 5 ns Synchronous mode; LDAC falling to WR rising 5
WR rising to LDAC rising (synchronous mode) t8 4.5 ns Synchronous mode; WR rising to LDAC rising 5
LDAC rising to WR rising (asynchronous mode) t9 5 ns Asynchronous mode; LDAC rising to WR rising 5
WR rising to LDAC falling (asynchronous mode) t10 4.5 ns Asynchronous mode; WR rising to LDAC falling 5
LDAC pulse width t11 20 ns LDAC pulse width 5
CLR pulse width t12 20 ns CLR pulse width 5
Time between WR cycles t13 50 ns Time between WR cycles 5
VDD to GND VDD -0.3 7 V Referenced to GND 6
Digital Input Voltage to GND -0.3 V Maximum printed as VDD + 0.3 V 6
Digital Output Voltage to GND -0.3 V Maximum printed as VDD + 0.3 V 6
Reference Input Voltage to GND -0.3 V Maximum printed as VDD + 0.3 V 6
VOUT to GND VOUT -0.3 V Maximum printed as VDD + 0.3 V 6
Operating Temperature Range (Industrial, B Version) -40 105 °C B Version 6
Storage Temperature Range -65 150 °C 6
Junction Temperature TJ 150 °C 6
Thermal Impedance θJA (20-Lead TSSOP) θJA 85 °C/W JEDEC 4-layer (2S2P) board; 20-lead TSSOP 6

CAD (KiCad official)

  • Symbol: AD5331BRUZ
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ad5331bruz-etched.step / ad5331bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5331bruz.step / ad5331bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 3cf624ce9f8b3fe8, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF