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AD5325BRMZ

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Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5325brmzfactory-2.0.0extractor-text

Verified AD5325BRMZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 10 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5325BRMZ · MSOP-10 · 10 pins
  • ✓copper: 10 copper pads, none touching another net
  • ✓datasheet: all 10 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C649585, digikey 505-AD5325BRMZ-ND, mouser 584-AD5325BRMZ
  • ✓family: MSOP-10_3x3mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-hxvzjfxj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.23)
  • ✓pads: 10 pins = 10 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 10 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5325brmz.kicad_sym✓ ad5325brmz.kicad_mod✓ ad5325brmz.step
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AD5325BRMZ

Analog Devices · Digital To Analog Converters (DACs) · MSOP-10

AD5325BRMZ from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input that can be operated from 2.5 V to 5.5 V and should be decoupled to GND.
2 VOUTA output Buffered analog output voltage from DAC A, with rail-to-rail operation of the output amplifier.
3 VOUTB output Buffered analog output voltage from DAC B, with rail-to-rail operation of the output amplifier.
4 VOUTC output Buffered analog output voltage from DAC C, with rail-to-rail operation of the output amplifier.
5 REFIN input Reference input pin for all four DACs, with an input range from 0.25 V to VDD.
6 VOUTD output Buffered analog output voltage from DAC D, with rail-to-rail operation of the output amplifier.
7 GND power_in Ground reference point for all circuitry on the part.
8 SDA bidirectional Bidirectional open-drain serial data line, used with SCL to clock data into or out of the 16-bit input shift register, that should be pulled to the supply with an external pull-up resistor.
9 SCL input Serial clock line, used with SDA to clock data into or out of the 16-bit input shift register, accommodating clock rates of up to 400 kb/s.
10 A0 input Address input that sets the least significant bit of the 7-bit slave address.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL), B version, AD5325 -10 2 10 LSB 3
Differential Nonlinearity, B version, AD5325 -1 0.2 1 LSB Guaranteed monotonic by design over all codes 3
Offset Error, B version -3 0.4 3 % of FSR 3
Gain Error, B version -1 0.15 1 % of FSR 3
Lower Deadband, B version 20 60 mV Lower deadband exists only if offset error is negative 3
VREF Input Range VREF 0.25 V 3
VREF Input Impedance, normal operation 37 45 kΩ Normal operation 3
VREF Input Impedance, power-down mode 10 MΩ Power-down mode 3
Input Low Voltage, A0 VIL 0.8 V VDD = 5 V ± 10% 4
Input Low Voltage, A0 VIL 0.6 V VDD = 3 V ± 10% 4
Input Low Voltage, A0 VIL 0.5 V VDD = 2.5 V 4
Input High Voltage, A0 VIH 2.4 V VDD = 5 V ± 10% 4
Input High Voltage, A0 VIH 2.1 V VDD = 3 V ± 10% 4
Input High Voltage, A0 VIH 2 V VDD = 2.5 V 4
Input Current, A0 -1 1 μA 4
Input Low Voltage, SCL/SDA VIL -0.3 V SMBus compatible at VDD < 3.6 V 4
Input Leakage Current, SCL/SDA IIN -1 1 μA 4
Output Low Voltage, SDA VOL 0.4 V ISINK = 3 mA 4
Output Low Voltage, SDA VOL 0.6 V ISINK = 6 mA 4
Three-State Leakage Current, SDA -1 1 μA 4
Supply Voltage VDD VDD 2.5 5.5 V 4
IDD Normal Mode IDD 600 900 μA VIH = VDD and VIL = GND; VDD = 4.5 V to 5.5 V 4
IDD Normal Mode IDD 500 700 μA VIH = VDD and VIL = GND; VDD = 2.5 V to 3.6 V 4
IDD Power-Down Mode IDD 0.2 1 μA VIH = VDD and VIL = GND; VDD = 4.5 V to 5.5 V 4
IDD Power-Down Mode IDD 0.08 1 μA VIH = VDD and VIL = GND; VDD = 2.5 V to 3.6 V 4
SCL Clock Frequency fSCL 400 kHz SCL clock frequency 5
SCL Cycle Time t1 2.5 μs 5
tHIGH, SCL High Time t2 0.6 μs 5
tLOW, SCL Low Time t3 1.3 μs 5
tHD,STA, Start/Repeated Start Hold Time t4 0.6 μs 5
tSU,DAT, Data Setup Time t5 100 ns 5
tHD,DAT, Data Hold Time t6 0.9 μs 5
tSU,STA, Repeated Start Setup Time t7 0.6 μs 5
tSU,STO, Stop Condition Setup Time t8 0.6 μs 5
tBUF, Bus-Free Time t9 1.3 μs 5
tR, Rise Time of SCL and SDA when receiving t10 300 ns 5
tF, Fall Time of SDA when transmitting t11 250 ns 5
tF, Fall Time of SCL and SDA when receiving 300 ns 5
Capacitive Load for Each Bus Line CB 400 pF 5
Output Voltage Settling Time, AD5325 8 10 μs VREF = VDD = 5 V; ¼ scale to ¾ scale change (0×400 to 0×C00) 5
VDD to GND VDD -0.3 7 V 7
Operating Temperature Range, Industrial (A, B Version) -40 105 °C 7
Storage Temperature Range -65 150 °C 7
Junction Temperature (TJ max) TJ 150 °C 7
Reflow Soldering Peak Temperature 220 °C 7
Offset Error Drift -12 ppm of FSR/°C 3
Gain Error Drift -5 ppm of FSR/°C 3
Power Supply Rejection Ratio PSRR -60 dB ΔVDD = ±10% 3
DC Crosstalk 200 μV RL = 2 kΩ to GND or VDD 3
DC Output Impedance 0.5 Ω 3
Short-Circuit Current 25 mA VDD = 5 V 3
Short-Circuit Current 16 mA VDD = 3 V 3
Power-Up Time 2.5 μs Coming out of power-down mode; VDD = 5 V 3
Power-Up Time 5 μs Coming out of power-down mode; VDD = 3 V 3
Minimum Output Voltage 0.001 V 3
Slew Rate 0.7 V/μs 5
Thermal Impedance, junction-to-ambient (MSOP) θJA 206 °C/W 7
Thermal Impedance, junction-to-case (MSOP) θJC 44 °C/W 7

CAD (KiCad official)

  • Symbol: AD5325BRMZ
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5325brmz-etched.step / ad5325brmz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5325brmz.step / ad5325brmz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 6a012b73f6a747d5, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF