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AD5318BRUZ

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-16

AD5318BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDAC input Active-low control input that transfers the input register contents to the DAC registers, or can be tied permanently low.
2 SYNC input Active-low frame synchronization input; data is clocked in on the following 16 falling SCLK edges, and a rising SYNC before the 16th edge causes the write to be ignored.
3 VDD power_in Power supply input operating from 2.5 V to 5.5 V, to be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4 VOUTA output Buffered analog output voltage from DAC A with rail-to-rail output amplifier operation.
5 VOUTB output Buffered analog output voltage from DAC B with rail-to-rail output amplifier operation.
6 VOUTC output Buffered analog output voltage from DAC C with rail-to-rail output amplifier operation.
7 VOUTD output Buffered analog output voltage from DAC D with rail-to-rail output amplifier operation.
8 VREFABCD input Reference input for DACs A to D, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
9 VREFEFGH input Reference input for DACs E to H, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
10 VOUTE output Buffered analog output voltage from DAC E with rail-to-rail output amplifier operation.
11 VOUTF output Buffered analog output voltage from DAC F with rail-to-rail output amplifier operation.
12 VOUTG output Buffered analog output voltage from DAC G with rail-to-rail output amplifier operation.
13 VOUTH output Buffered analog output voltage from DAC H with rail-to-rail output amplifier operation.
14 GND power_in Ground reference point for all circuitry on the part.
15 DIN input Serial data input to a 16-bit shift register, clocked on the falling edge of SCLK, with the input buffer powered down after each write cycle.
16 SCLK input Serial clock input for clocking data into the input shift register on falling edges, with transfer rates up to 30 MHz.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

CAD (KiCad official)

  • Symbol: AD5318BRUZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad5318bruz-etched.step / ad5318bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5318bruz.step / ad5318bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 54d929c54190959e, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF