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Ray Set visibility: public 2631cab 5d ago
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{
  "schema_version": 1,
  "type": "component",
  "slug": "ad5318aruz-reel7",
  "title": "AD5318ARUZ-REEL7",
  "brief": "Analog Devices Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "data acquisition",
    "ad5318aruz-reel7",
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  "component": {
    "mpn": "AD5318ARUZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590224653315698688",
    "parts": {
      "symbol": "ad5318aruz-reel7.kicad_sym",
      "footprint": "ad5318aruz-reel7.kicad_mod",
      "model_3d": "ad5318aruz-reel7-hero.glb",
      "model_3d_plain": "ad5318aruz-reel7-etched.glb",
      "model_3d_step": "ad5318aruz-reel7-etched.step",
      "model_3d_step_plain": "ad5318aruz-reel7.step",
      "lbr": "ad5318aruz-reel7.lbr"
    },
    "distributor_links": {
      "lcsc": "C515875",
      "digikey": "AD5318ARUZ-REEL7TR-ND",
      "mouser": "584-AD5318ARUZ-R7"
    },
    "distributor_check": {
      "checked_at": "2026-10-21T01:18:13Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AD5318ARUZ-REEL7TR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD5318ARUZ-R7",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "LDAC",
        "type": "input",
        "description": "This active low control input transfers the contents of the input registers to their respective DAC registers, and it may alternatively be tied permanently low."
      },
      {
        "number": "2",
        "name": "SYNC",
        "type": "input",
        "description": "Active low frame synchronization input: data is clocked in on the falling edges of the following 16 clocks, and a rising edge of SYNC before the 16th falling edge causes the write sequence to be ignored."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input that can be operated from 2.5 V to 5.5 V and should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND."
      },
      {
        "number": "4",
        "name": "VOUTA",
        "type": "output",
        "description": "Buffered analog output voltage from DAC A, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "5",
        "name": "VOUTB",
        "type": "output",
        "description": "Buffered analog output voltage from DAC B, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "6",
        "name": "VOUTC",
        "type": "output",
        "description": "Buffered analog output voltage from DAC C, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "7",
        "name": "VOUTD",
        "type": "output",
        "description": "Buffered analog output voltage from DAC D, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "8",
        "name": "VREFABCD",
        "type": "input",
        "description": "Reference input for DACs A, B, C and D, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode."
      },
      {
        "number": "9",
        "name": "VREFEFGH",
        "type": "input",
        "description": "Reference input for DACs E, F, G and H, with an input range of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode."
      },
      {
        "number": "10",
        "name": "VOUTE",
        "type": "output",
        "description": "Buffered analog output voltage from DAC E, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "11",
        "name": "VOUTF",
        "type": "output",
        "description": "Buffered analog output voltage from DAC F, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "12",
        "name": "VOUTG",
        "type": "output",
        "description": "Buffered analog output voltage from DAC G, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "13",
        "name": "VOUTH",
        "type": "output",
        "description": "Buffered analog output voltage from DAC H, with an output amplifier that has rail-to-rail operation."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
      },
      {
        "number": "15",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to a 16-bit shift register, clocked in on the falling edge of SCLK; the DIN input buffer is powered down after each write cycle."
      },
      {
        "number": "16",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input, with data clocked into the input shift register on the falling edge at rates up to 30 MHz; the SCLK input buffer is powered down after each write cycle."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 10,
        "cost_usd": 0.0596,
        "at": "2026-10-21T01:15:32"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590224653315698688",
        "pages": 28,
        "sha256": "54d929c54190959e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ad5318aruz-reel7.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ad5318aruz-reel7-etched.step",
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        "origin": "footprint origin = pad-pattern centre",
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    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-16",
      "Category": "Data Acquisition",
      "Pins": "16"
    },
    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "datasheet_sha256": "54d929c54190959e3cc25d1b0f0f6f32db5ae4a79c2226bde8ca039f8985731a",
      "rows": [
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          "name": "Relative Accuracy (AD5318, A version)",
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          "kind": "electrical",
          "unit": "LSB",
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          "typ": 0.5,
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          "name": "Differential Nonlinearity (AD5318, A version)",
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          "conditions": "Guaranteed monotonic by design over all codes",
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          "max": null,
          "conditions": "Unbuffered reference mode; printed upper limit is VDD",
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          "name": "VREF Input Impedance (RDAC), buffered and power-down mode",
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          "name": "VREF Input Impedance (RDAC), unbuffered, 0 V to VREF output range",
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          "typ": null,
          "max": 45,
          "conditions": "Unbuffered reference mode, 0 V to VREF output range",
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        {
          "name": "VREF Input Impedance (RDAC), unbuffered, 0 V to 2 VREF output range",
          "symbol": "RDAC",
          "kind": "electrical",
          "unit": "kΩ",
          "min": 18,
          "typ": null,
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          "conditions": "Unbuffered reference mode, 0 V to 2 VREF output range",
          "source_page": 4,
          "source": "datasheet"
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        {
          "name": "Minimum Output Voltage",
          "symbol": "",
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          "min": 0.001,
          "typ": null,
          "max": null,
          "conditions": "Drive capability of the output amplifier",
          "source_page": 4,
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        },
        {
          "name": "Input Current",
          "symbol": "",
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          "unit": "μA",
          "min": -1,
          "typ": null,
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        },
        {
          "name": "VIL, Input Low Voltage",
          "symbol": "VIL",
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          "min": null,
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          "max": 0.8,
          "conditions": "VDD = 5 V ± 10%",
          "source_page": 5,
          "source": "datasheet"
        },
        {
          "name": "VIL, Input Low Voltage",
          "symbol": "VIL",
          "kind": "electrical",
          "unit": "V",
          "min": null,
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          "max": 0.7,
          "conditions": "VDD = 2.5 V",
          "source_page": 5,
          "source": "datasheet"
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        {
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          "typ": null,
          "max": null,
          "conditions": "VDD = 2.5 V to 5.5 V, TTL and CMOS compatible",
          "source_page": 5,
          "source": "datasheet"
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        {
          "name": "Supply Voltage",
          "symbol": "VDD",
          "kind": "recommended_operating",
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          "max": 5.5,
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        {
          "name": "IDD (Normal Mode)",
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          "max": 1.8,
          "conditions": "VIH = VDD and VIL = GND; VDD = 4.5 V to 5.5 V; all DACs in unbuffered mode, in buffered mode",
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        {
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          "typ": 0.7,
          "max": 1.5,
          "conditions": "VIH = VDD and VIL = GND; VDD = 2.5 V to 3.6 V",
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        {
          "name": "IDD (Power-Down Mode)",
          "symbol": "IDD",
          "kind": "electrical",
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          "min": null,
          "typ": 0.4,
          "max": 1,
          "conditions": "VIH = VDD and VIL = GND; all eight DACs powered down; VDD = 4.5 V to 5.5 V",
          "source_page": 5,
          "source": "datasheet"
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        {
          "name": "IDD (Power-Down Mode)",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "μA",
          "min": null,
          "typ": 0.12,
          "max": 1,
          "conditions": "VIH = VDD and VIL = GND; all eight DACs powered down; VDD = 2.5 V to 3.6 V",
          "source_page": 5,
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        {
          "name": "Output Voltage Settling Time (AD5318)",
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          "typ": 7,
          "max": 9,
          "conditions": "VREF = VDD = 5 V; 1/4 scale to 3/4 scale change (0x100 To 0x300)",
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        {
          "name": "SCLK cycle time",
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          "kind": "timing",
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          "conditions": "SCLK cycle time",
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        {
          "name": "SCLK high time",
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          "kind": "timing",
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          "max": null,
          "conditions": "SCLK high time",
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          "name": "SCLK low time",
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          "min": 13,
          "typ": null,
          "max": null,
          "conditions": "SCLK low time",
          "source_page": 6,
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        },
        {
          "name": "SYNC to SCLK falling edge setup time",
          "symbol": "t4",
          "kind": "timing",
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          "min": 13,
          "typ": null,
          "max": null,
          "conditions": "Temperature range (A, B version): −40°C to +105°C",
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        {
          "name": "SYNC to SCLK falling edge setup time",
          "symbol": "t4",
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          "min": 15,
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          "max": null,
          "conditions": "Temperature range (A, B version): −40°C to +125°C",
          "source_page": 6,
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        {
          "name": "Data set up time",
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          "conditions": "Data set up time",
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          "name": "Data hold time",
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          "conditions": "Data hold time",
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        {
          "name": "SCLK falling edge to SYNC rising edge",
          "symbol": "t7",
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          "conditions": "SCLK falling edge to SYNC rising edge",
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        {
          "name": "Minimum SYNC high time",
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          "typ": null,
          "max": null,
          "conditions": "Minimum SYNC high time",
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        {
          "name": "LDAC pulse width",
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          "min": 20,
          "typ": null,
          "max": null,
          "conditions": "LDAC pulse width",
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        {
          "name": "SCLK falling edge to LDAC rising edge",
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          "kind": "timing",
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          "typ": null,
          "max": null,
          "conditions": "SCLK falling edge to LDAC rising edge",
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        {
          "name": "SCLK falling edge to LDAC falling edge",
          "symbol": "t11",
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          "typ": null,
          "max": null,
          "conditions": "SCLK falling edge to LDAC falling edge",
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        },
        {
          "name": "VDD to GND",
          "symbol": "VDD",
          "kind": "absolute_maximum",
          "unit": "V",
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          "typ": null,
          "max": 7,
          "conditions": "TA = 25°C",
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        {
          "name": "Digital Input Voltage to GND",
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          "conditions": "TA = 25°C; printed upper limit is VDD + 0.3 V",
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        {
          "name": "Reference Input Voltage to GND",
          "symbol": "",
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          "conditions": "TA = 25°C; printed upper limit is VDD + 0.3 V",
          "source_page": 7,
          "source": "datasheet"
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