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AD5317RBCPZ-RL7

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Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5317rbcpz-rl7factory-2.0.0extractor-text

Verified AD5317RBCPZ-RL7

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5317RBCPZ-RL7 · LFCSP-16(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 28-page datasheet
  • ✓distributor: lcsc C649566, digikey AD5317RBCPZ-RL7TR-ND, mouser 584-AD5317RBCPZ-R7
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-smtobc9y/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5317rbcpz-rl7.kicad_sym✓ ad5317rbcpz-rl7.kicad_mod✓ ad5317rbcpz-rl7.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 2d ago
viewers ad5317rbcpz-rl7: viewers · Ray 2d ago
ad5317rbcpz-rl7-etched.glb Publish 0.1.0 · Ray 2d ago
ad5317rbcpz-rl7-etched.step ad5317rbcpz-rl7: factory component page (tier=mfr) · Ray 2d ago
ad5317rbcpz-rl7-hero.glb ad5317rbcpz-rl7: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
ad5317rbcpz-rl7-hero.overlay.json Publish 0.1.0 · Ray 2d ago
ad5317rbcpz-rl7.glb Publish 0.1.0 · Ray 2d ago
ad5317rbcpz-rl7.kicad_mod Publish 0.1.0 · Ray 2d ago
ad5317rbcpz-rl7.kicad_sym Publish 0.1.0 · Ray 2d ago
ad5317rbcpz-rl7.lbr Publish 0.1.0 · Ray 2d ago
ad5317rbcpz-rl7.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray 2d ago

AD5317RBCPZ-RL7

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)

AD5317RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A with rail-to-rail output amplifier.
2 GND power_in Ground reference point for all circuitry on the part.
3 VDD power_in Power supply input, 2.7 V to 5.5 V, decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 VOUTC output Analog output voltage from DAC C with rail-to-rail output amplifier.
5 VOUTD output Analog output voltage from DAC D with rail-to-rail output amplifier.
6 SDO output Serial data output for daisy-chaining or readback; data transfers on the rising edge of SCLK and is valid on the falling edge of the clock.
7 LDAC input Load DAC input operated asynchronously or synchronously; pulsing low updates DAC registers with new input register data, and it can be tied permanently low.
8 GAIN input Span set pin: tied to GND gives 0 V to VREF output span, tied to VLOGIC gives 0 V to 2 × VREF for all four DACs.
9 VLOGIC power_in Digital power supply, voltage range 1.62 V to 5.5 V.
10 SCLK input Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 50 MHz.
11 SYNC input Active-low frame synchronization input; when low, data is transferred in on the falling edges of the next 24 clocks.
12 SDIN input Serial data input to the 24-bit input shift register, clocked in on the falling edge of the serial clock.
13 RESET input Asynchronous falling-edge-sensitive reset input that loads zero scale or midscale per RSTSEL and ignores LDAC pulses while low; tie to VLOGIC if unused.
14 RSTSEL input Power-on reset select: tied to GND powers up all four DACs to zero scale, tied to VLOGIC powers up to midscale.
15 VREF power_in Common reference pin: reference output when using the internal reference (default), reference input when using an external reference.
16 VOUTB output Analog output voltage from DAC B with rail-to-rail output amplifier.
17 EPAD passive Exposed pad; must be tied to GND.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-16(3x3)
Category ADC/DAC/Data Conversion
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy INL -0.5 0.12 0.5 LSB 3
Differential Nonlinearity DNL -0.5 0.5 LSB Guaranteed monotonic by design 3
Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register 3
Offset Error -1.5 0.1 1.5 mV 3
Full-Scale Error -0.1 0.01 0.1 % of FSR All 1s loaded to DAC register 3
Gain Error -0.1 0.02 0.1 % of FSR 3
Load Regulation (5 V) 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA 3
Load Regulation (3 V) 80 µV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA 3
Resistive Load 1 kΩ 3
Reference Output Voltage 2.4975 2.5025 V At ambient 3
Reference TC 2 5 ppm/°C See the Terminology section 3
Reference Output Current Load Capability -5 5 mA VDD ≥ 3 V 3
Logic Input Current -2 2 µA Per pin 3
Output Low Voltage VOL 0.4 V ISINK = 200 μA 3
VLOGIC VLOGIC 1.62 5.5 V 4
ILOGIC ILOGIC 3 µA 4
VDD VDD 2.7 5.5 V Gain = 1 4
IDD Normal Mode IDD 0.59 0.7 mA Internal reference off; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V 4
IDD Normal Mode, reference on IDD 1.1 1.3 mA Internal reference on, at full scale; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V 4
IDD All Power-Down Modes IDD 1 4 µA −40°C to +85°C 4
IDD All Power-Down Modes (hot) IDD 6 µA −40°C to +105°C 4
Output Voltage Settling Time 5 7 µs ¼ to ¾ scale settling to ±1 LSB 5
SCLK Cycle Time t1 20 ns 2.7 V ≤ VLOGIC ≤ 5.5 V 5
SCLK High Time t2 10 ns 2.7 V ≤ VLOGIC ≤ 5.5 V 5
SCLK Low Time t3 10 ns 2.7 V ≤ VLOGIC ≤ 5.5 V 5
Power-Up Time (timing) 4.5 µs 2.7 V ≤ VLOGIC ≤ 5.5 V 5
Offset Error Drift 1 µV/°C 3
Gain Temperature Coefficient 1 ppm Of FSR/°C 3
DC Power Supply Rejection Ratio 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% 3
Short-Circuit Current 40 mA VDD = 5 V 3
VDD to GND VDD -0.3 7 V 8
VLOGIC to GND VLOGIC -0.3 7 V 8
Operating Temperature Range -40 105 °C 8
Storage Temperature Range -65 150 °C 8
Junction Temperature 125 °C 8
Reflow Soldering Peak Temperature, Pb Free 260 °C J-STD-020 8
16-Lead LFCSP θJA Thermal Impedance θJA 70 °C/W 0 Airflow (4-Layer Board) 8

CAD (KiCad official)

  • Symbol: AD5317RBCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: ad5317rbcpz-rl7-etched.step / ad5317rbcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5317rbcpz-rl7.step / ad5317rbcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 6462567adde833e1, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF