component
AD5313RBCPZ-RL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAD5313RBCPZ-RL7
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)
AD5313RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A with rail-to-rail output amplifier. |
| 2 | GND | power_in | Ground reference point for all circuitry on the AD5313R. |
| 3 | VDD | power_in | Power supply input, 2.7 V to 5.5 V, decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. |
| 4 | NC | unconnected | No connect; do not connect to this pin. |
| 5 | VOUTB | output | Analog output voltage from DAC B with rail-to-rail output amplifier. |
| 6 | SDO | output | Serial data output used for daisy-chaining devices or readback; data transferred on the rising edge of SCLK and valid on the falling edge. |
| 7 | LDAC | input | Load DAC input operating in asynchronous or synchronous mode; pulsing low updates DAC registers, and it can be tied permanently low. |
| 8 | GAIN | input | Gain select: tied to GND gives 0 V to VREF output span, tied to VLOGIC gives 0 V to 2 × VREF. |
| 9 | VLOGIC | power_in | Digital power supply, 1.62 V to 5.5 V. |
| 10 | SCLK | input | Serial clock input; data is clocked into the shift register on the falling edge at up to 50 MHz. |
| 11 | SYNC | input | Active-low frame synchronization input; when low, data is transferred in on the falling edges of the next 24 clocks. |
| 12 | SDIN | input | Serial data input to the 24-bit input shift register, clocked on the falling edge of SCLK. |
| 13 | RESET | input | Asynchronous falling-edge-sensitive reset input that loads zero scale or midscale per RSTSEL and ignores LDAC pulses while low; tie to VLOGIC if unused. |
| 14 | RSTSEL | input | Power-on reset select: tied to GND powers up both DACs to zero scale, tied to VLOGIC to midscale. |
| 15 | VREF | power_in | Common reference pin; reference output when using the internal reference (default) and reference input when using an external reference. |
| 16 | NC | unconnected | No connect; do not connect to this pin. |
| 17 | EPAD | power_in | Exposed pad; must be tied to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | INL | -0.5 | 0.12 | 0.5 | LSB | 3 | |
| Differential Nonlinearity | DNL | -0.5 | 0.5 | LSB | Guaranteed monotonic by design | 3 | |
| Zero-Code Error | 0.4 | 1.5 | mV | All 0s loaded to DAC register | 3 | ||
| Offset Error | -1.5 | 0.1 | 1.5 | mV | 3 | ||
| Full-Scale Error | -0.1 | 0.01 | 0.1 | % of FSR | All 1s loaded to DAC register | 3 | |
| Gain Error | -0.1 | 0.02 | 0.1 | % of FSR | 3 | ||
| Reference Output Voltage | VREF | 2.4975 | 2.5025 | V | At ambient | 3 | |
| Reference Temperature Coefficient | 2 | 5 | ppm/°C | See the Terminology section | 3 | ||
| Logic Input Current | -2 | 2 | µA | Per pin | 3 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 200 µA | 4 | ||
| Logic Supply Voltage | VLOGIC | 1.62 | 5.5 | V | 4 | ||
| Logic Supply Current | ILOGIC | 3 | µA | 4 | |||
| Supply Voltage | VDD | 2.7 | 5.5 | V | Gain = 1 | 4 | |
| Supply Current, Normal Mode, Reference Off | IDD | 0.59 | 0.7 | mA | Internal reference off; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V | 4 | |
| Supply Current, Normal Mode, Reference On | IDD | 1.1 | 1.3 | mA | Internal reference on, at full scale; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V | 4 | |
| Supply Current, Power-Down | IDD | 1 | 4 | µA | All power-down modes; −40°C to +85°C | 4 | |
| Supply Current, Power-Down | IDD | 6 | µA | All power-down modes; −40°C to +105°C | 4 | ||
| Output Voltage Settling Time | 5 | 7 | µs | ¼ to ¾ scale settling to ±2 LSB | 4 | ||
| SCLK Cycle Time | t1 | 20 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| SCLK High Time | t2 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| SCLK Low Time | t3 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| SYNC to SCLK Falling Edge Setup Time | t4 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| Data Setup Time | t5 | 5 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| Data Hold Time | t6 | 5 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| SCLK Falling Edge to SYNC Rising Edge | t7 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| Minimum SYNC High Time | t8 | 20 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 | ||
| VDD to GND | VDD | -0.3 | 7 | V | TA = 25°C | 8 | |
| VLOGIC to GND | VLOGIC | -0.3 | 7 | V | TA = 25°C | 8 | |
| VOUT to GND (lower bound; upper is VDD + 0.3 V) | VOUT | -0.3 | V | TA = 25°C | 8 | ||
| VREF to GND (lower bound; upper is VDD + 0.3 V) | VREF | -0.3 | V | TA = 25°C | 8 | ||
| Digital Input Voltage to GND (lower bound; upper is VLOGIC + 0.3 V) | -0.3 | V | TA = 25°C | 8 | |||
| Operating Temperature Range | -40 | 105 | °C | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Junction Temperature | 125 | °C | 8 | ||||
| Reflow Soldering Peak Temperature, Pb Free | 260 | °C | J-STD-020 | 8 | |||
| ESD (HBM) | 4 | kV | Human body model classification | 8 | |||
| Thermal Impedance, 16-Lead LFCSP | θJA | 70 | °C/W | 0 Airflow (4-Layer Board) | 8 | ||
| Offset Error Drift | 1 | µV/°C | 3 | ||||
| Gain Temperature Coefficient | 1 | ppm Of FSR/°C | 3 | ||||
| DC Power Supply Rejection Ratio | PSRR | 0.15 | mV/V | DAC code = midscale; VDD = 5 V ± 10% | 3 | ||
| Short-Circuit Current | 40 | mA | VDD = 5 V | 3 | |||
| Load Impedance at Rails | 25 | Ω | See Figure 28 | 3 | |||
| Reference Output Impedance | 0.04 | Ω | 3 | ||||
| Slew Rate | 0.8 | V/µs | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | Human body model (HBM) classification. Stresses at or above those listed under Absolute Maximum | 8 |
CAD (KiCad official)
- Symbol:
AD5313RBCPZ-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5313rbcpz-rl7-etched.step/ad5313rbcpz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5313rbcpz-rl7.step/ad5313rbcpz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (26 pp, sha256
3f4b4dc2530a6412, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).