component
AD5308ARUZ
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+178−8@@ -1,13 +1,188 @@ {+ "schema_version": 1,+ "type": "component", "slug": "ad5308aruz",+ "title": "AD5308ARUZ",+ "brief": "Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "adc-dac-data conversion", "ad5308aruz" ],+ "component": {+ "mpn": "AD5308ARUZ",+ "manufacturer": "Analog Devices",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Digital To Analog Converters (DACs)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589802375193538560",+ "parts": {+ "symbol": "ad5308aruz.kicad_sym",+ "footprint": "ad5308aruz.kicad_mod",+ "model_3d": "ad5308aruz.glb",+ "model_3d_step": "ad5308aruz.step",+ "lbr": "ad5308aruz.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "LDAC",+ "type": "input",+ "description": "Active-low load-DAC control input. Pulsing this pin low transfers the contents of the input registers to their DAC registers, allowing simultaneous update of any or all DAC outputs. May be tied permanently low for asynchronous updates."+ },+ {+ "number": "2",+ "name": "SYNC",+ "type": "input",+ "description": "Active-low frame synchronization input for the serial interface. When SYNC goes low it powers on the SCLK and DIN buffers and enables the input shift register; taking SYNC high before the 16th falling clock aborts the write."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply input, 2.5 V to 5.5 V. Decouple with a 10 uF capacitor in parallel with a 0.1 uF capacitor to GND close to the pin."+ },+ {+ "number": "4",+ "name": "VOUTA",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel A. Rail-to-rail operation; drives 2 kOhm/200 pF loads."+ },+ {+ "number": "5",+ "name": "VOUTB",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel B. Rail-to-rail operation."+ },+ {+ "number": "6",+ "name": "VOUTC",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel C. Rail-to-rail operation."+ },+ {+ "number": "7",+ "name": "VOUTD",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel D. Rail-to-rail operation."+ },+ {+ "number": "8",+ "name": "VREFABCD",+ "type": "input",+ "description": "Reference input for DACs A, B, C and D. Configurable as buffered, unbuffered, or VDD input via the BUF/VDD control bits. Input range 0.25 V to VDD in unbuffered mode, 1 V to VDD in buffered mode."+ },+ {+ "number": "9",+ "name": "VREFEFGH",+ "type": "input",+ "description": "Reference input for DACs E, F, G and H. Configurable as buffered, unbuffered, or VDD input via the BUF/VDD control bits. Input range 0.25 V to VDD in unbuffered mode, 1 V to VDD in buffered mode."+ },+ {+ "number": "10",+ "name": "VOUTE",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel E. Rail-to-rail operation."+ },+ {+ "number": "11",+ "name": "VOUTF",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel F. Rail-to-rail operation."+ },+ {+ "number": "12",+ "name": "VOUTG",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel G. Rail-to-rail operation."+ },+ {+ "number": "13",+ "name": "VOUTH",+ "type": "output",+ "description": "Buffered analog output voltage from DAC channel H. Rail-to-rail operation."+ },+ {+ "number": "14",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for all circuitry on the part."+ },+ {+ "number": "15",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input. The device has a 16-bit shift register; data is clocked in on the falling edge of SCLK. The DIN input buffer is powered down after each write cycle."+ },+ {+ "number": "16",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input. Data is clocked into the input shift register on the falling edge at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589802375193538560",+ "pages": 28,+ "sha256": "54d929c54190959e",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Analog Devices",+ "Package": "TSSOP-16",+ "Category": "ADC/DAC/Data Conversion",+ "Pins": "16"+ }+ },+ "variants": [+ {+ "mpn": "AD5308ARUZ",+ "kind": "packaging"+ },+ {+ "mpn": "AD5308ARUZBRUZ",+ "kind": "packaging"+ },+ {+ "mpn": "AD5308ARUZBRU",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "ad5308aruz"+ ],+ "discovery_pitch": "AD5308ARUZ (Analog Devices) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +200,5 @@ "docs/ad5308aruz-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }