Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

AD5308ARUZ

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-16

AD5308ARUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDAC input Active-low load-DAC control input. Pulsing this pin low transfers the contents of the input registers to their DAC registers, allowing simultaneous update of any or all DAC outputs. May be tied permanently low for asynchronous updates.
2 SYNC input Active-low frame synchronization input for the serial interface. When SYNC goes low it powers on the SCLK and DIN buffers and enables the input shift register; taking SYNC high before the 16th falling clock aborts the write.
3 VDD power_in Power supply input, 2.5 V to 5.5 V. Decouple with a 10 uF capacitor in parallel with a 0.1 uF capacitor to GND close to the pin.
4 VOUTA output Buffered analog output voltage from DAC channel A. Rail-to-rail operation; drives 2 kOhm/200 pF loads.
5 VOUTB output Buffered analog output voltage from DAC channel B. Rail-to-rail operation.
6 VOUTC output Buffered analog output voltage from DAC channel C. Rail-to-rail operation.
7 VOUTD output Buffered analog output voltage from DAC channel D. Rail-to-rail operation.
8 VREFABCD input Reference input for DACs A, B, C and D. Configurable as buffered, unbuffered, or VDD input via the BUF/VDD control bits. Input range 0.25 V to VDD in unbuffered mode, 1 V to VDD in buffered mode.
9 VREFEFGH input Reference input for DACs E, F, G and H. Configurable as buffered, unbuffered, or VDD input via the BUF/VDD control bits. Input range 0.25 V to VDD in unbuffered mode, 1 V to VDD in buffered mode.
10 VOUTE output Buffered analog output voltage from DAC channel E. Rail-to-rail operation.
11 VOUTF output Buffered analog output voltage from DAC channel F. Rail-to-rail operation.
12 VOUTG output Buffered analog output voltage from DAC channel G. Rail-to-rail operation.
13 VOUTH output Buffered analog output voltage from DAC channel H. Rail-to-rail operation.
14 GND power_in Ground reference for all circuitry on the part.
15 DIN input Serial data input. The device has a 16-bit shift register; data is clocked in on the falling edge of SCLK. The DIN input buffer is powered down after each write cycle.
16 SCLK input Serial clock input. Data is clocked into the input shift register on the falling edge at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • AD5308ARUZ
  • AD5308ARUZBRUZ
  • AD5308ARUZBRU

CAD (KiCad official)

  • Symbol: AD5308ARUZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad5308aruz-etched.step / ad5308aruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5308aruz.step / ad5308aruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 54d929c54190959e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF