# AD5304ARMZ-REEL7

**Analog Devices** · Digital To Analog Converters (DACs) · MSOP-10

AD5304ARMZ-REEL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input; the part operates from 2.5 V to 5.5 V and the supply can be decoupled to GND. |
| 2 | VOUTA | output | Buffered analog output voltage from DAC A, driven by a rail-to-rail output amplifier. |
| 3 | VOUTB | output | Buffered analog output voltage from DAC B, driven by a rail-to-rail output amplifier. |
| 4 | VOUTC | output | Buffered analog output voltage from DAC C, driven by a rail-to-rail output amplifier. |
| 5 | REFIN | input | Reference input for all four DACs with an input range from 0.25 V to VDD. |
| 6 | VOUTD | output | Buffered analog output voltage from DAC D, driven by a rail-to-rail output amplifier. |
| 7 | GND | power_in | Ground reference point for all circuitry on the part. |
| 8 | DIN | input | Serial data input to a 16-bit shift register, clocked in on the falling edge of SCLK; the input buffer powers down after each write cycle. |
| 9 | SCLK | input | Serial clock input that clocks data into the shift register on its falling edge at speeds up to 30 MHz; the input buffer powers down after each write cycle. |
| 10 | SYNC | input | Active-low frame synchronization input that enables the shift register when low; if taken high before the 16th SCLK falling edge, the write sequence is ignored. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy |  | -1 | 0.15 | 1 | LSB |  | 3 |
| Differential Nonlinearity |  | -0.25 | 0.02 | 0.25 | LSB | Guaranteed monotonic by design over all codes | 3 |
| Offset Error |  | -3 | 0.4 | 3 | % of FSR | See Figure 13 and Figure 14 | 3 |
| Gain Error |  | -1 | 0.15 | 1 | % of FSR | See Figure 13 and Figure 14 | 3 |
| Lower Dead Band |  |  | 20 | 60 | mV | Lower dead band exists only if offset error is negative | 3 |
| VREF Input Range |  | 0.25 |  |  | V |  | 3 |
| VREF Input Impedance |  | 37 | 45 |  | kΩ | Normal operation | 3 |
| VREF Input Impedance (power-down) |  | 10 |  |  | MΩ | Power-down mode | 3 |
| Logic Input Current |  | -1 |  | 1 | µA |  | 4 |
| Input Low Voltage | VIL |  |  | 0.8 | V | VDD = 5 V ± 10% | 4 |
| Input Low Voltage | VIL |  |  | 0.6 | V | VDD = 3 V ± 10% | 4 |
| Input Low Voltage | VIL |  |  | 0.5 | V | VDD = 2.5 V | 4 |
| Input High Voltage | VIH | 2.4 |  |  | V | VDD = 5 V ± 10% | 4 |
| Input High Voltage | VIH | 2.1 |  |  | V | VDD = 3 V ± 10% | 4 |
| Input High Voltage | VIH | 2 |  |  | V | VDD = 2.5 V | 4 |
| Supply Voltage | VDD | 2.5 |  | 5.5 | V |  | 4 |
| Normal Mode Supply Current | IDD |  | 600 | 900 | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 4 |
| Normal Mode Supply Current | IDD |  | 500 | 700 | µA | VDD = 2.5 V to 3.6 V; VIH = VDD and VIL = GND | 4 |
| Power-Down Mode Supply Current | IDD |  | 0.2 | 1 | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 4 |
| Power-Down Mode Supply Current | IDD |  | 0.08 | 1 | µA | VDD = 2.5 V to 3.6 V; VIH = VDD and VIL = GND | 4 |
| Output Voltage Settling Time (AD5304) |  |  | 6 | 8 | µs | VREF = VDD = 5 V; ¼ scale to ¾ scale change (0x40 to 0xC0) | 4 |
| Supply Voltage VDD to GND | VDD | -0.3 |  | 7 | V |  | 6 |
| Digital Input Voltage to GND |  | -0.3 |  |  | V | Maximum given as VDD + 0.3 V | 6 |
| Reference Input Voltage to GND |  | -0.3 |  |  | V | Maximum given as VDD + 0.3 V | 6 |
| VOUTA through VOUTD to GND |  | -0.3 |  |  | V | Maximum given as VDD + 0.3 V | 6 |
| Operating Temperature Range |  | -40 |  | 105 | °C | Industrial (A, B, W Version) | 6 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 6 |
| Junction Temperature (TJ max) | TJ |  |  | 150 | °C |  | 6 |
| Reflow Peak Temperature |  |  |  | 260 | °C | Pb-free | 6 |
| Thermal Impedance junction-to-ambient (10-Lead MSOP) | θJA |  | 206 |  | °C/W | 10-Lead MSOP | 6 |
| Thermal Impedance junction-to-case (10-Lead MSOP) | θJC |  | 44 |  | °C/W | 10-Lead MSOP | 6 |

## CAD (KiCad official)

- Symbol: `AD5304ARMZ-REEL7`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `ad5304armz-reel7-etched.step` / `ad5304armz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5304armz-reel7.step` / `ad5304armz-reel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5304_5314_5324.pdf) (24 pp, sha256 `bc06ab85376cc929`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5304armz-reel7-datasheet.pdf)