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AD5300BRTZ-REEL7

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Analog Devices Digital To Analog Converters (DACs), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD5300BRTZ-REEL7

Analog Devices · Digital To Analog Converters (DACs) · SOT-23-6

AD5300BRTZ-REEL7 from Analog Devices, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output Analog output voltage from the DAC, driven by an output amplifier with rail-to-rail operation over 0 V to VDD.
2 GND power_in Ground reference point for all circuitry on the part.
3 VDD power_in Power supply input, stated in the pin table as operable from 2.5 V to 5.5 V, which should be decoupled to GND.
4 DIN input Serial data input to a 16-bit shift register, with data clocked in on the falling edge of SCLK.
5 SCLK input Serial clock input that clocks data into the input shift register on its falling edge, at rates up to 30 MHz.
6 SYNC input Active-low level-triggered frame synchronization input; the DAC updates after the 16th clock cycle unless SYNC is taken high first, which aborts the write.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOT-23-6
Category ADC/DAC/Data Conversion
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy -1 1 LSB See Figure 2. 2
Differential Nonlinearity -0.25 0.25 LSB Guaranteed Monotonic by Design. See Figure 3. 2
Zero-Code Error 0.5 3.5 LSB All Zeros Loaded to DAC Register. See Figure 6. 2
Full-Scale Error -0.5 -3.5 LSB All Ones Loaded to DAC Register. See Figure 6. 2
Gain Error -1.25 1.25 % of FSR 2
Zero-Code Error Drift -20 µV/°C 2
Gain Temperature Coefficient -5 ppm of FSR/°C 2
Output Voltage Range 0 V 2
Output Voltage Settling Time 4 6 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex). RL = 2 kΩ; 0 pF < CL < 500 pF. See Figure 16. 2
Slew Rate 1 V/µs 2
Capacitive Load Stability 470 pF RL = ∞ 2
Capacitive Load Stability 1000 pF RL = 2 kΩ 2
Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB Change Around Major Carry. See Figure 19. 2
Digital Feedthrough 0.5 nV-s 2
DC Output Impedance 1 Ω 2
Short-Circuit Current 50 mA VDD = 5 V. 2
Short-Circuit Current 20 mA VDD = 3 V. 2
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V. 2
Power-Up Time 5 µs Coming Out of Power-Down Mode. VDD = 3 V. 2
Input Current -1 1 µA 2
VINL, Input Low Voltage VINL 0.8 V VDD = 5 V. 2
VINL, Input Low Voltage VINL 0.6 V VDD = 3 V. 2
VINH, Input High Voltage VINH 2.4 V VDD = 5 V. 2
VINH, Input High Voltage VINH 2.1 V VDD = 3 V. 2
Pin Capacitance 3 pF 2
VDD Supply Voltage VDD 2.7 5.5 V 2
IDD Normal Mode IDD 140 250 µA DAC Active and Excluding Load Current. VDD = 4.5 V to 5.5 V. VIH = VDD and VIL = GND. 2
IDD Normal Mode IDD 115 200 µA DAC Active and Excluding Load Current. VDD = 2.7 V to 3.6 V. VIH = VDD and VIL = GND. 2
IDD All Power-Down Modes IDD 0.2 1 µA VDD = 4.5 V to 5.5 V. VIH = VDD and VIL = GND. 2
IDD All Power-Down Modes IDD 0.05 1 µA VDD = 2.7 V to 3.6 V. VIH = VDD and VIL = GND. 2
Power Efficiency IOUT/IDD 93 % ILOAD = 2 mA. VDD = 5 V. 2
SCLK Cycle Time t1 50 ns VDD = 2.7 V to 3.6 V 3
SCLK Cycle Time t1 33 ns VDD = 3.6 V to 5.5 V 3
SCLK High Time t2 13 ns VDD = 2.7 V to 3.6 V 3
SCLK Low Time t3 22.5 ns VDD = 2.7 V to 3.6 V 3
SCLK Low Time t3 13 ns VDD = 3.6 V to 5.5 V 3
SYNC to SCLK Falling Edge Setup Time t4 13 ns VDD = 2.7 V to 3.6 V 3
Data Setup Time t5 55 ns 3
Data Hold Time t6 4.5 ns VDD = 2.7 V to 3.6 V 3
SCLK Falling Edge to SYNC Rising Edge t7 0 ns VDD = 2.7 V to 3.6 V 3
Minimum SYNC High Time t8 50 ns VDD = 2.7 V to 3.6 V 3
Minimum SYNC High Time t8 33 ns VDD = 3.6 V to 5.5 V 3
VDD to GND VDD -0.3 7 V 3
Digital Input Voltage to GND -0.3 V 3
VOUT to GND VOUT -0.3 V 3
Operating Temperature Range -40 105 °C Industrial (B Version) 3
Storage Temperature Range -65 150 °C 3
Junction Temperature (TJ max) TJ 150 °C 3
θJA Thermal Impedance, SOT-23 Package θJA 240 °C/W SOT-23 Package 3

CAD (KiCad official)

  • Symbol: AD5300BRTZ-REEL7
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: ad5300brtz-reel7-etched.step / ad5300brtz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5300brtz-reel7.step / ad5300brtz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (13 pp, sha256 40ad52511094615d, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF