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AD5293BRUZ-50-RL7

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Analog Devices Digital Potentiometers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5293bruz-50-rl7factory-2.0.0extractor-text

Verified AD5293BRUZ-50-RL7

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5293BRUZ-50-RL7 · TSSOP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C649501, digikey 505-AD5293BRUZ-50-RL7TR-ND, mouser 584-AD5293BRUZ-50-R7
  • ✓family: TSSOP-14_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_qgdi5g0/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5293bruz-50-rl7.kicad_sym✓ ad5293bruz-50-rl7.kicad_mod✓ ad5293bruz-50-rl7.step
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Ray Publish 0.1.0 00e8e10 17h ago

AD5293BRUZ-50-RL7

Analog Devices · Digital Potentiometers · TSSOP-14

AD5293BRUZ-50-RL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET input Hardware reset pin that sets the RDAC register to midscale on a logic high transition, and should be tied to VLOGIC if not used.
2 VSS power_in Negative supply that connects to 0 V for single-supply applications and should be decoupled with 0.1 µF ceramic and 10 µF capacitors.
3 A passive Terminal A of the RDAC, with VSS ≤ VA ≤ VDD.
4 W passive Wiper terminal W of the RDAC, with VSS ≤ VW ≤ VDD.
5 B passive Terminal B of the RDAC, with VSS ≤ VB ≤ VDD.
6 VDD power_in Positive power supply that should be decoupled with 0.1 µF ceramic and 10 µF capacitors.
7 EXT_CAP passive Connection for a 1 µF capacitor that must have a voltage rating of ≥7 V.
8 VLOGIC power_in Logic power supply operating from 2.7 V to 5.5 V, decoupled with 0.1 µF ceramic and 10 µF capacitors.
9 GND power_in Ground pin that serves as the logic ground reference.
10 DIN input Serial data input to a 16-bit shift register, with data clocked in on the falling edge of the serial clock.
11 SCLK input Serial clock input that supports data transfer rates up to 50 MHz, with data clocked into the shift register on the falling edge.
12 SYNC input Active-low frame synchronization input that enables the shift register; the selected register updates on the rising edge following the 16th clock, and an earlier rising edge causes the write sequence to be ignored.
13 SDO output Open-drain serial data output that requires an external pull-up resistor and is used for daisy-chain or readback mode.
14 RDY output Active-high open-drain ready output that identifies completion of a write or read operation to or from the RDAC register.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-14
Category ADC/DAC/Data Conversion
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Resistor Differential Nonlinearity R-DNL -1 1 LSB RWB 5
Resistor Integral Nonlinearity R-INL -2 2 LSB 5
Nominal Resistor Tolerance (R-Perf Mode) ΔRAB/RAB -1 0.5 1 % See Table 4 5
Nominal Resistor Tolerance (Normal Mode) ΔRAB/RAB -20 20 % 5
Differential Nonlinearity DNL -1 1 LSB 5
Integral Nonlinearity INL -1.5 1.5 LSB 5
Full-Scale Error VWFSE -8 1 LSB Code = full scale 5
Zero-Scale Error VWZSE 0 8 LSB Code = zero scale 5
Common-Mode Leakage Current ICM -1 1 nA VA = VB = VW 5
Input Logic High VIH 2 V VLOGIC = 2.7 V to 5.5 V 5
Input Logic Low VIL 0.8 V VLOGIC = 2.7 V to 5.5 V 5
Input Current IIL -1 1 µA VIN = 0 V or VLOGIC 5
Tristate Leakage Current -1 1 µA 5
Single-Supply Power Range VDD 9 33 V VSS = 0 V 5
Dual-Supply Power Range VDD/VSS 9 16.5 V 5
Positive Supply Current IDD 0.1 2 µA VDD/VSS = ±16.5 V 5
Negative Supply Current ISS -2 -0.1 µA VDD/VSS = ±16.5 V 5
Logic Supply Range VLOGIC 2.7 5.5 V 5
Logic Supply Current ILOGIC 1 10 µA VLOGIC = 5 V; VIH = 5 V or VIL = GND 5
Power Dissipation PDISS 8 110 µW VIH = 5 V or VIL = GND 5
Wiper Resistance RW 60 100 Ω 5
Interface SCLK cycle time t1 20 ns SCLK cycle time 7
Interface SCLK high time t2 10 ns SCLK high time 7
Interface SCLK low time t3 10 ns SCLK low time 7
SYNC to SCLK falling edge setup time t4 10 ns 7
Data setup time t5 5 ns 7
Data hold time t6 5 ns 7
SYNC rise to RDY fall time t11 40 ns 7
RDY low time, RDAC write execute time (resistor performance mode) t12 2.4 µs resistor performance mode 7
RDY low time, RDAC write execute time (normal mode) t12 410 ns normal mode 7
RDY low time, RDAC register read command execute time t13 450 ns 7
SCLK rising edge to SDO valid t14 450 ns 7
Software/hardware reset t12 1.5 ms 7
Minimum RESET pulse width (asynchronous) tRESET 20 ns 7
Power-on time to half scale tPOWER-UP 2 ms 7
VDD to GND VDD -0.3 35 V 9
VSS to GND VSS -25 0.3 V 9
VLOGIC to GND VLOGIC -0.3 7 V 9
VDD to VSS VDD-VSS 35 V 9
EXT_CAP voltage to GND EXT_CAP -0.3 7 V 9
Continuous current IA, IB, IW IA, IB, IW -2 2 mA Continuous, RAB = 50 kΩ, 100 kΩ 9
Operating Temperature Range TA -40 105 °C 9
Maximum Junction Temperature TJ max 150 °C 9
Storage Temperature Range -65 150 °C 9
Nominal end-to-end resistance RAB 50 kΩ 50 kΩ version 1
Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT × 10^6 5 ppm/°C Code = half scale 5
Resistance Temperature Coefficient (ΔRAB/RAB)/ΔT × 10^6 35 ppm/°C 5
Capacitance A, Capacitance B CA, CB 85 pF f = 1 MHz, measured to GND, code = half-scale 5
Capacitance W CW 65 pF f = 1 MHz, measured to GND, code = half-scale 5
Input Capacitance CIL 5 pF 5
Output Capacitance COL 5 pF 5
Bandwidth BW 210 kHz −3 dB, RAB = 50 kΩ 6
Bandwidth BW 105 kHz −3 dB, RAB = 100 kΩ 6
Resistor Noise Density eN_WB 18 nV/√Hz Code = half scale, TA = 25°C, 0 kHz to 200 kHz, RAB = 50 kΩ 6
Resistor Noise Density eN_WB 27 nV/√Hz Code = half scale, TA = 25°C, 0 kHz to 200 kHz, RAB = 100 kΩ 6
Thermal Resistance Junction-to-Case, 14-Lead TSSOP θJC 20 °C/W 9

CAD (KiCad official)

  • Symbol: AD5293BRUZ-50-RL7
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: ad5293bruz-50-rl7-etched.step / ad5293bruz-50-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5293bruz-50-rl7.step / ad5293bruz-50-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 717f5791e0c7ebf3, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF