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AD5270BRMZ-100
Public Made by Adomby adom
Analog Devices Digital Potentiometers, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5270BRMZ-100
Analog Devices · Digital Potentiometers · MSOP-10
AD5270BRMZ-100 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors, 2.7 V to 5.5 V single-supply. |
| 2 | A | passive | Terminal A of RDAC; VSS ≤ VA ≤ VDD. |
| 3 | W | passive | Wiper terminal of RDAC; VSS ≤ VW ≤ VDD. |
| 4 | VSS | power_in | Negative supply; connect to 0 V for single-supply applications and decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 5 | EXT_CAP | passive | External capacitor pin; connect a 1 µF capacitor between EXT_CAP and VSS with a voltage rating of ≥7 V. |
| 6 | GND | power_in | Ground pin, logic ground reference. |
| 7 | SDO | output | Serial data output for daisy-chain or readback mode; open-drain output requiring an external pull-up resistor even if not used. |
| 8 | DIN | input | Serial data line used with SCLK to clock data into or out of the 16-bit input register. |
| 9 | SCLK | input | Serial clock input; data is clocked into the shift register on the falling edge, at rates up to 50 MHz. |
| 10 | SYNC | input | Falling-edge frame synchronization signal for input data; the register is updated on the rising edge after the 16th clock, and taking it high before the 16th clock causes the write to be ignored. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Integral Nonlinearity | R-INL | -1 | 1 | LSB | RAW = 50 kΩ, 100 kΩ | 3 | |
| Resistor Differential Nonlinearity | R-DNL | -1 | 1 | LSB | 3 | ||
| Nominal Resistor Tolerance, R-Perf Mode | -1 | 0.5 | 1 | % | See Table 2 and Table 3 | 3 | |
| Nominal Resistor Tolerance, Normal Mode | -15 | 15 | % | 3 | |||
| Wiper Resistance | 35 | 70 | Ω | Code = zero scale | 3 | ||
| Input Logic High | VINH | 2 | V | 3 | |||
| Input Logic Low | VINL | 0.8 | V | 3 | |||
| Input Current | IIN | -1 | 1 | µA | 3 | ||
| Output Voltage Low | VOL | 0.4 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.7 V to 5.5 V, VSS = 0 V | 3 | ||
| Output Voltage Low | VOL | 0.6 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V | 3 | ||
| Tristate Leakage Current | -1 | 1 | µA | 3 | |||
| Single-Supply Power Range | VDD | 2.7 | 5.5 | V | VSS = 0 V | 3 | |
| Supply Current Positive | IDD | 1 | µA | 3 | |||
| Supply Current Negative | ISS | -1 | µA | 3 | |||
| 50-TP Store Current Positive | IDD_OTP_STORE | 4 | mA | 3 | |||
| 50-TP Store Current Negative | ISS_OTP_STORE | -4 | mA | 3 | |||
| OTP Read Current Positive | IDD_OTP_READ | 500 | µA | 3 | |||
| OTP Read Current Negative | ISS_OTP_READ | -500 | µA | 3 | |||
| Power Dissipation | 5.5 | µW | VIH = VDD or VIL = GND | 3 | |||
| Power Supply Rejection Ratio | PSRR | -78 | -70 | dB | ΔVDD/ΔVSS = ±5 V ± 10%, RAW = 100 kΩ | 4 | |
| Resistance Temperature Coefficient | 5 | ppm/°C | Code = full scale | 3 | |||
| Capacitance A | 90 | pF | f = 1 MHz, measured to GND, code = half scale | 3 | |||
| Capacitance W | 40 | pF | f = 1 MHz, measured to GND, code = half scale | 3 | |||
| Common-Mode Leakage Current | 50 | nA | VA = VW | 3 | |||
| Input Capacitance | CIN | 5 | pF | 3 | |||
| Output Capacitance | 5 | pF | 3 | ||||
| Bandwidth | 60 | kHz | −3 dB, RAW = 100 kΩ, Terminal W | 4 | |||
| Total Harmonic Distortion | -85 | dB | VA = 1 V rms, f = 1 kHz, code = half scale, RAW = 100 kΩ | 4 | |||
| Resistor Noise Density | 32 | nV/√Hz | Code = half scale, TA = 25°C, RAW = 100 kΩ | 4 | |||
| SCLK cycle time | t1 | 20 | ns | 6 | |||
| SCLK high time | t2 | 10 | ns | 6 | |||
| SCLK low time | t3 | 10 | ns | 6 | |||
| SYNC to SCLK falling edge setup time | t4 | 15 | ns | 6 | |||
| Data setup time | t5 | 5 | ns | 6 | |||
| Data hold time | t6 | 5 | ns | 6 | |||
| SCLK falling edge to SYNC rising edge | t7 | 1 | ns | 7 | |||
| Minimum SYNC high time | t8 | 500 | ns | 7 | |||
| SYNC rising edge to next SCLK fall ignored | t9 | 15 | ns | 7 | |||
| SCLK rising edge to SDO valid | t10 | 450 | ns | RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF | 7 | ||
| RDAC register write command execute time (R-Perf) | tRDAC_R-PERF | 2 | µs | 7 | |||
| RDAC register write command execute time (Normal) | tRDAC_NORMAL | 600 | ns | 7 | |||
| Memory readback execute time | tMEMORY_READ | 6 | µs | 7 | |||
| Memory program time | tMEMORY_PROGRAM | 350 | ms | 7 | |||
| Reset 50-TP restore time | tRESET | 0.6 | ms | 7 | |||
| Power-on 50-TP restore time | tPOWER-UP | 2 | ms | Maximum time after VDD − VSS is equal to 2.5 V | 7 | ||
| VDD to GND | VDD | -0.3 | 7 | V | TA = 25°C | 8 | |
| VSS to GND | VSS | -7 | 0.3 | V | TA = 25°C | 8 | |
| VDD to VSS | 7 | V | TA = 25°C | 8 | |||
| EXT_CAP to VSS | 7 | V | TA = 25°C | 8 | |||
| Continuous current IA, IW | IA, IW | -2 | 2 | mA | RAW = 50 kΩ, 100 kΩ | 8 | |
| Operating Temperature Range | -40 | 125 | °C | Includes programming of 50-TP memory | 8 | ||
| Maximum Junction Temperature | TJ max | 150 | °C | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Reflow Soldering Peak Temperature | 260 | °C | Time at peak 20 sec to 40 sec | 8 | |||
| Thermal Resistance Junction to Ambient | θJA | 161.8 | °C/W | 10-Lead MSOP | 8 | ||
| Thermal Resistance Junction to Board | θJB | 25.2 | °C/W | 10-Lead MSOP | 8 |
CAD (KiCad official)
- Symbol:
AD5270BRMZ-100 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5270brmz-100-etched.step/ad5270brmz-100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5270brmz-100.step/ad5270brmz-100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
7856686a104180a6, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5270BRMZ-100
**Analog Devices** · Digital Potentiometers · MSOP-10
AD5270BRMZ-100 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors, 2.7 V to 5.5 V single-supply. |
| 2 | A | passive | Terminal A of RDAC; VSS ≤ VA ≤ VDD. |
| 3 | W | passive | Wiper terminal of RDAC; VSS ≤ VW ≤ VDD. |
| 4 | VSS | power_in | Negative supply; connect to 0 V for single-supply applications and decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 5 | EXT_CAP | passive | External capacitor pin; connect a 1 µF capacitor between EXT_CAP and VSS with a voltage rating of ≥7 V. |
| 6 | GND | power_in | Ground pin, logic ground reference. |
| 7 | SDO | output | Serial data output for daisy-chain or readback mode; open-drain output requiring an external pull-up resistor even if not used. |
| 8 | DIN | input | Serial data line used with SCLK to clock data into or out of the 16-bit input register. |
| 9 | SCLK | input | Serial clock input; data is clocked into the shift register on the falling edge, at rates up to 50 MHz. |
| 10 | SYNC | input | Falling-edge frame synchronization signal for input data; the register is updated on the rising edge after the 16th clock, and taking it high before the 16th clock causes the write to be ignored. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Integral Nonlinearity | R-INL | -1 | | 1 | LSB | RAW = 50 kΩ, 100 kΩ | 3 |
| Resistor Differential Nonlinearity | R-DNL | -1 | | 1 | LSB | | 3 |
| Nominal Resistor Tolerance, R-Perf Mode | | -1 | 0.5 | 1 | % | See Table 2 and Table 3 | 3 |
| Nominal Resistor Tolerance, Normal Mode | | -15 | | 15 | % | | 3 |
| Wiper Resistance | | | 35 | 70 | Ω | Code = zero scale | 3 |
| Input Logic High | VINH | 2 | | | V | | 3 |
| Input Logic Low | VINL | | | 0.8 | V | | 3 |
| Input Current | IIN | -1 | | 1 | µA | | 3 |
| Output Voltage Low | VOL | | | 0.4 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.7 V to 5.5 V, VSS = 0 V | 3 |
| Output Voltage Low | VOL | | | 0.6 | V | RPULL_UP = 2.2 kΩ to VDD, VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V | 3 |
| Tristate Leakage Current | | -1 | | 1 | µA | | 3 |
| Single-Supply Power Range | VDD | 2.7 | | 5.5 | V | VSS = 0 V | 3 |
| Supply Current Positive | IDD | | | 1 | µA | | 3 |
| Supply Current Negative | ISS | -1 | | | µA | | 3 |
| 50-TP Store Current Positive | IDD_OTP_STORE | | | 4 | mA | | 3 |
| 50-TP Store Current Negative | ISS_OTP_STORE | -4 | | | mA | | 3 |
| OTP Read Current Positive | IDD_OTP_READ | | | 500 | µA | | 3 |
| OTP Read Current Negative | ISS_OTP_READ | -500 | | | µA | | 3 |
| Power Dissipation | | | | 5.5 | µW | VIH = VDD or VIL = GND | 3 |
| Power Supply Rejection Ratio | PSRR | | -78 | -70 | dB | ΔVDD/ΔVSS = ±5 V ± 10%, RAW = 100 kΩ | 4 |
| Resistance Temperature Coefficient | | | 5 | | ppm/°C | Code = full scale | 3 |
| Capacitance A | | | 90 | | pF | f = 1 MHz, measured to GND, code = half scale | 3 |
| Capacitance W | | | 40 | | pF | f = 1 MHz, measured to GND, code = half scale | 3 |
| Common-Mode Leakage Current | | | 50 | | nA | VA = VW | 3 |
| Input Capacitance | CIN | | 5 | | pF | | 3 |
| Output Capacitance | | | 5 | | pF | | 3 |
| Bandwidth | | | 60 | | kHz | −3 dB, RAW = 100 kΩ, Terminal W | 4 |
| Total Harmonic Distortion | | | -85 | | dB | VA = 1 V rms, f = 1 kHz, code = half scale, RAW = 100 kΩ | 4 |
| Resistor Noise Density | | | 32 | | nV/√Hz | Code = half scale, TA = 25°C, RAW = 100 kΩ | 4 |
| SCLK cycle time | t1 | 20 | | | ns | | 6 |
| SCLK high time | t2 | 10 | | | ns | | 6 |
| SCLK low time | t3 | 10 | | | ns | | 6 |
| SYNC to SCLK falling edge setup time | t4 | 15 | | | ns | | 6 |
| Data setup time | t5 | 5 | | | ns | | 6 |
| Data hold time | t6 | 5 | | | ns | | 6 |
| SCLK falling edge to SYNC rising edge | t7 | 1 | | | ns | | 7 |
| Minimum SYNC high time | t8 | 500 | | | ns | | 7 |
| SYNC rising edge to next SCLK fall ignored | t9 | 15 | | | ns | | 7 |
| SCLK rising edge to SDO valid | t10 | | | 450 | ns | RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF | 7 |
| RDAC register write command execute time (R-Perf) | tRDAC_R-PERF | | | 2 | µs | | 7 |
| RDAC register write command execute time (Normal) | tRDAC_NORMAL | | | 600 | ns | | 7 |
| Memory readback execute time | tMEMORY_READ | | | 6 | µs | | 7 |
| Memory program time | tMEMORY_PROGRAM | | | 350 | ms | | 7 |
| Reset 50-TP restore time | tRESET | | | 0.6 | ms | | 7 |
| Power-on 50-TP restore time | tPOWER-UP | | | 2 | ms | Maximum time after VDD − VSS is equal to 2.5 V | 7 |
| VDD to GND | VDD | -0.3 | | 7 | V | TA = 25°C | 8 |
| VSS to GND | VSS | -7 | | 0.3 | V | TA = 25°C | 8 |
| VDD to VSS | | | | 7 | V | TA = 25°C | 8 |
| EXT_CAP to VSS | | | | 7 | V | TA = 25°C | 8 |
| Continuous current IA, IW | IA, IW | -2 | | 2 | mA | RAW = 50 kΩ, 100 kΩ | 8 |
| Operating Temperature Range | | -40 | | 125 | °C | Includes programming of 50-TP memory | 8 |
| Maximum Junction Temperature | TJ max | | | 150 | °C | | 8 |
| Storage Temperature Range | | -65 | | 150 | °C | | 8 |
| Reflow Soldering Peak Temperature | | | | 260 | °C | Time at peak 20 sec to 40 sec | 8 |
| Thermal Resistance Junction to Ambient | θJA | | 161.8 | | °C/W | 10-Lead MSOP | 8 |
| Thermal Resistance Junction to Board | θJB | | 25.2 | | °C/W | 10-Lead MSOP | 8 |
## CAD (KiCad official)
- Symbol: `AD5270BRMZ-100`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `ad5270brmz-100-etched.step` / `ad5270brmz-100-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5270brmz-100.step` / `ad5270brmz-100.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5270_5271.pdf) (24 pp, sha256 `7856686a104180a6`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5270brmz-100-datasheet.pdf)