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AD5259BRMZ50-R7

Analog Devices · Digital Potentiometers · MSOP-10

AD5259BRMZ50-R7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 W passive W terminal (wiper), with GND ≤ VW ≤ VDD.
2 AD0 input Programmable address pin 0 for multiple package decoding; its state is registered on power-up.
3 AD1 input Programmable address pin 1 for multiple package decoding; its state is registered on power-up.
4 SDA bidirectional Serial data input/output for the I2C-compatible interface.
5 SCL input Serial clock input, positive edge triggered.
6 VLOGIC power_in Logic power supply, 2.7 V to 5.5 V.
7 GND power_in Digital ground.
8 VDD power_in Positive power supply, 2.7 V to 5.5 V.
9 B passive B terminal, with GND ≤ VB ≤ VDD.
10 A passive A terminal, with GND ≤ VA ≤ VDD.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category Data Converters
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal end-to-end resistance RAB 50 kΩ AD5259BRMZ50-R7 RAB option 21
Nominal Resistor Tolerance ΔRAB -30 30 % TA = 25°C, VDD = 5.5 V 3
Resistor DNL (50 kΩ/100 kΩ) R-DNL -0.5 0.1 0.5 LSB RWB, VA = no connect 3
Resistor INL (50 kΩ/100 kΩ) R-INL -1 0.4 1 LSB RWB, VA = no connect 3
Total Wiper Resistance RWB 75 350 Ω Code = 0x00 3
Differential Nonlinearity (50 kΩ/100 kΩ) DNL -0.5 0.2 0.5 LSB Potentiometer divider mode 3
Integral Nonlinearity (50 kΩ/100 kΩ) INL -0.5 0.1 0.5 LSB Potentiometer divider mode 3
Full-Scale Error (50 kΩ/100 kΩ) VWFSE -1 -0.4 0 LSB Code = 0xFF 3
Zero-Scale Error (50 kΩ/100 kΩ) VWZSE 0 0.2 0.5 LSB Code = 0x00 3
Input Logic Low VIL -0.5 V Max is 0.3 × VL as printed 4
Leakage Current SDA, AD0, AD1 IIL -1 0.01 1 µA VIN = 0 V or 5 V 4
Leakage Current SCL, Logic High IIL -2.5 -1.3 1 µA VIN = 0 V 4
Leakage Current SCL, Logic Low IIL -1 0.01 1 µA VIN = 5 V 4
Power Supply Range VDD 2.7 5.5 V 4
Positive Supply Current IDD 0.1 2 µA 4
Logic Supply VLOGIC 2.7 5.5 V 4
Logic Supply Current ILOGIC 3 6 µA VIH = 5 V or VIL = 0 V, −40°C < TA < +85°C 4
Logic Supply Current (hot) ILOGIC 9 µA VIH = 5 V or VIL = 0 V, +85°C < TA < +125°C 4
Programming Mode Current (EEPROM) ILOGIC(PROG) 35 mA VIH = 5 V or VIL = 0 V 4
Power Dissipation PDISS 15 40 µW VIH = 5 V or VIL = 0 V, VDD = 5 V 4
Power Supply Rejection Ratio PSRR -0.06 0.005 0.06 %/% VDD = +5 V ± 10%, code = 0x80 4
Capacitance A, B CA,B 45 pF f = 1 MHz, measured to GND, code = 0x80 3
Capacitance W CW 60 pF f = 1 MHz, measured to GND, code = 0x80 3
Input Capacitance CIL 5 pF 4
Bandwidth −3 dB BW 160 kHz Code = 0x80, RAB = 50 kΩ 4
Total Harmonic Distortion THDW 0.01 % RAB = 10 kΩ, VA = 1 V rms, VB = 0, f = 1 kHz 4
VW Settling Time tS 500 ns RAB = 10 kΩ, VAB = 5 V, ±1 LSB error band 4
Resistor Noise Voltage Density eN_WB 9 nV/√Hz RWB = 5 kΩ, f = 1 kHz 4
SCL Clock Frequency fSCL 0 400 kHz 4
Bus Free Time Between Stop and Start t1 1.3 µs 4
Hold Time (Repeated Start) t2 0.6 µs After this period, the first clock pulse is generated. 4
Low Period of SCL Clock t3 1.3 µs 4
High Period of SCL Clock t4 0.6 µs 4
Setup Time for Repeated Start Condition t5 0.6 µs 4
Data Hold Time t6 0 0.9 µs 4
Data Setup Time t7 100 ns 4
Fall Time of SDA and SCL t8 300 ns 5
Rise Time of SDA and SCL t9 300 ns 5
Setup Time for Stop Condition t10 0.6 µs 5
EEPROM Data Storing Time tEEMEM_STORE 26 ms 5
EEPROM Data Restoring Time at Power-On tEEMEM_RESTORE1 300 µs VDD rise time dependent. Measure without decoupling capacitors at VDD and GND. 5
EEPROM Data Restoring Time upon Restore Command tEEMEM_RESTORE2 300 µs VDD = 5 V. 5
EEPROM Data Rewritable Time tEEMEM_REWRITE 540 µs 5
Endurance 100 700 kCycles 5
Data Retention 100 Years 5
VDD, VLOGIC to GND VDD, VLOGIC -0.3 7 V TA = 25°C 6
Pulsed terminal current IMAX -20 20 mA Pulsed 6
Continuous terminal current IMAX -5 5 mA Continuous 6
Digital Inputs and Output Voltage to GND 0 7 V 6
Operating Temperature Range -40 125 °C 6
Maximum Junction Temperature TJMAX 150 °C 6
Storage Temperature -65 150 °C 6
Lead Temperature (Soldering, 10 sec) 300 °C 6
Junction to ambient thermal resistance, 10-Lead MSOP θJA 169.8 °C/W JEDEC 2S2P board, simulated 6
Junction to board thermal resistance, 10-Lead MSOP θJB 104.2 °C/W JEDEC 2S2P board, simulated 6

CAD (KiCad official)

  • Symbol: AD5259BRMZ50-R7
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad5259brmz50-r7-etched.step / ad5259brmz50-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5259brmz50-r7.step / ad5259brmz50-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 f1e0a0033b37a670, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF