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AD5254BRUZ100-RL7

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Analog Devices Digital Potentiometers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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AD5254BRUZ100-RL7

Analog Devices · Digital Potentiometers · TSSOP-20

AD5254BRUZ100-RL7 from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 W0 passive Wiper terminal of RDAC0, with VSS ≤ VW0 ≤ VDD.
2 B0 passive B terminal of RDAC0, with VSS ≤ VB0 ≤ VDD.
3 A0 passive A terminal of RDAC0, with VSS ≤ VA0 ≤ VDD.
4 AD0 input I2C device address 0; AD0 and AD1 together allow four AD5253/AD5254 devices to be addressed.
5 WP input Write protect, active low, with VWP ≤ VDD + 0.3 V.
6 W1 passive Wiper terminal of RDAC1, with VSS ≤ VW1 ≤ VDD.
7 B1 passive B terminal of RDAC1, with VSS ≤ VB1 ≤ VDD.
8 A1 passive A terminal of RDAC1, with VSS ≤ VA1 ≤ VDD.
9 SDA bidirectional Serial data input/output that shifts in one bit at a time on positive clock edges with MSB loaded first; open-drain MOSFET requires a pull-up resistor.
10 VSS power_in Negative supply, connected to 0 V for single supply or -2.7 V for dual supply, where VDD - VSS ≤ +5.5 V; if used rather than grounded in dual supply, it must sink 35 mA for 26 ms when storing data to EEMEM.
11 A2 passive A terminal of RDAC2, with VSS ≤ VA2 ≤ VDD.
12 B2 passive B terminal of RDAC2, with VSS ≤ VB2 ≤ VDD.
13 W2 passive Wiper terminal of RDAC2, with VSS ≤ VW2 ≤ VDD.
14 SCL input Serial input register clock that shifts in one bit at a time on positive clock edges, with VSCL ≤ (VDD + 0.3 V); a pull-up resistor is recommended to ensure minimum power.
15 DGND power_in Digital ground, to be connected to system analog ground at a single point.
16 AD1 input I2C device address 1; AD0 and AD1 together allow four AD5253/AD5254 devices to be addressed.
17 A3 passive A terminal of RDAC3, with VSS ≤ VA3 ≤ VDD.
18 B3 passive B terminal of RDAC3, with VSS ≤ VB3 ≤ VDD.
19 W3 passive Wiper terminal of RDAC3, with VSS ≤ VW3 ≤ VDD.
20 VDD power_in Positive supply, connected to +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where VDD - VSS ≤ +5.5 V; must source 35 mA for 26 ms when storing data to EEMEM.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20
Category ADC/DAC/Data Conversion
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal end-to-end resistance RAB (100 kΩ option) RAB 100 kΩ 1
Nominal resistor tolerance ΔRAB/RAB -20 20 % TA = 25°C 5
Resistance temperature coefficient (ΔRAB/RAB) × 10^6/ΔT 650 ppm/°C 5
Resistor Differential Nonlinearity (AD5254) R-DNL -1 0.25 1 LSB RWB, RWA = NC 4
Resistor Nonlinearity (AD5254) R-INL -2.5 1 2.5 LSB RWB, RWA = NC 5
Wiper Resistance RW 75 130 Ω IW = 1 V/R, VDD = 5 V 5
Wiper Resistance RW 200 300 Ω IW = 1 V/R, VDD = 3 V 5
Channel-Resistance Matching ΔRAB1/ΔRAB2 0.05 % RAB = 100 kΩ 5
Differential Nonlinearity (AD5254) DNL -1 0.3 1 LSB 5
Integral Nonlinearity (AD5254) INL -1.5 0.5 1.5 LSB 5
Full-Scale Error (AD5254) VWFSE -3 -1 0 LSB Code = full scale 5
Zero-Scale Error (AD5254) VWZSE 0 1.2 3 LSB Code = zero scale 5
Common-Mode Leakage Current ICM 0.01 1 µA VA = VB = VDD/2 5
Input Logic High VIH 2.4 V VDD = 5 V, VSS = 0 V 5
Input Logic High VIH 2.1 V VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V 5
Input Logic Low VIL 0.8 V VDD = 5 V, VSS = 0 V 5
Input Logic Low VIL 0.6 V VDD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V 5
Output Logic High (SDA) VOH 4.9 V RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 5
Output Logic Low (SDA) VOL 0.4 V RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 5
WP Leakage Current IWP 8 µA WP = VDD 5
A0 Leakage Current IA0 3 µA A0 = GND 5
Input Leakage Current (other than WP and A0) II -1 1 µA VIN = 0 V or VDD 5
Single-Supply Power Range VDD 2.7 5.5 V VSS = 0 V 5
Dual-Supply Power Range VDD/VSS 2.25 2.75 V 5
Positive Supply Current IDD 5 15 µA VIH = VDD or VIL = GND 5
Negative Supply Current ISS -5 -15 µA VIH = VDD or VIL = GND, VDD = 2.5 V, VSS = −2.5 V 5
EEMEM Data Storing Mode Current IDD_STORE 35 mA VIH = VDD or VIL = GND, TA = 0°C to 105°C 5
EEMEM Data Restoring Mode Current IDD_RESTORE 2.5 mA VIH = VDD or VIL = GND, TA = 0°C to 105°C 5
Power Supply Sensitivity PSS -0.005 0.002 0.005 %/% ΔVDD = 5 V ± 10% 5
Power Supply Sensitivity PSS -0.01 0.002 0.01 %/% ΔVDD = 3 V ± 10% 5
SCL Clock Frequency fSCL 400 kHz 6
Bus-Free Time Between Stop and Start tBUF 1.3 µs 6
Hold Time (Repeated Start) tHD;STA 0.6 µs After this period, the first clock pulse is generated. 6
Low Period of SCL Clock tLOW 1.3 µs 6
High Period of SCL Clock tHIGH 0.6 µs 6
Set-up Time for Start Condition tSU;STA 0.6 µs 6
Data Hold Time tHD;DAT 0 0.9 µs 6
Data Set-up Time tSU;DAT 100 ns 6
Fall Time of Both SDA and SCL Signals tF 300 ns 6
Rise Time of Both SDA and SCL Signals tR 300 ns 6
Set-up Time for Stop Condition tSU;STO 0.6 µs 6
Endurance 100 K cycles 7
VDD to GND -0.3 7 V 8
VSS to GND -7 0.3 V 8
VDD to VSS 7 V 8
Maximum current IWB, IWA pulsed IWB, IWA -20 20 mA Pulsed 8
Maximum continuous current IWB IWB -5 5 mA RWB ≤ 1 kΩ, A Open 8
Maximum continuous current IWA IWA -5 5 mA RWA ≤ 1 kΩ, B Open 8
Maximum continuous current IAB IAB -50 50 µA RAB = 100 kΩ 8
Digital inputs and output voltage to GND 0 7 V 8
Operating Temperature Range -40 105 °C 8
Maximum Junction Temperature TJMAX 150 °C 8
Storage Temperature Range -65 150 °C 8
Lead Temperature (Soldering) 300 °C 10 sec 8
Lead Temperature (Vapor Phase) 215 °C 60 sec 8
Lead Temperature (Infrared) 220 °C 15 sec 8
Thermal resistance junction-to-ambient (TSSOP-20) θJA 143 °C/W 8

CAD (KiCad official)

  • Symbol: AD5254BRUZ100-RL7
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ad5254bruz100-rl7-etched.step / ad5254bruz100-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5254bruz100-rl7.step / ad5254bruz100-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (26 pp, sha256 e604eaabdc343b78, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF