component
AD5247BKSZ100-RL7
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5247BKSZ100-RL7
Analog Devices · Pre-ordered Chips · SC-70-6
AD5247BKSZ100-RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply, specified for single-supply operation from 2.7 V to 5.5 V. |
| 2 | GND | power_in | Digital ground and B terminal voltage reference. |
| 3 | SCL | input | Serial clock input for the I2C-compatible interface, positive edge triggered. |
| 4 | SDA | bidirectional | Serial data input/output for the I2C-compatible interface. |
| 5 | W | passive | Terminal W, the wiper terminal of the resistor. |
| 6 | A | passive | Terminal A, one end terminal of the resistor, with no polarity limitation relative to W. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Interface ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Differential Nonlinearity | R-DNL | -1 | 0.1 | 1 | LSB | RWB, VA = no connect | 4 |
| Resistor Integral Nonlinearity | R-INL | -2 | 0.25 | 2 | LSB | RWB, VA = no connect | 4 |
| Nominal Resistor Tolerance | ∆RAB | -20 | 20 | % | VA = VDD, wiper (VW) = no connect | 4 | |
| Differential Nonlinearity | DNL | -1 | 0.1 | 1 | LSB | 4 | |
| Integral Nonlinearity | INL | -1 | 0.2 | 1 | LSB | 4 | |
| Output Resistance | RWB | 75 | 300 | Ω | RWB Code = 0x00 | 4 | |
| Full-Scale Error (50 kΩ, 100 kΩ) | VWFSE | -1 | -1 | 0 | LSB | Code = 0x7F | 4 |
| Zero-Scale Error (50 kΩ, 100 kΩ) | VWZSE | 0 | 0.4 | 1 | LSB | Code = 0x00 | 4 |
| Input Logic High (VDD = 5 V) | VIH | 2.4 | V | VDD = 5 V | 4 | ||
| Input Logic Low (VDD = 5 V) | VIL | 0.8 | V | VDD = 5 V | 4 | ||
| Input Logic High (VDD = 3 V) | VIH | 2.1 | V | VDD = 3 V | 4 | ||
| Input Logic Low (VDD = 3 V) | VIL | 0.6 | V | VDD = 3 V | 4 | ||
| Input Current | IIL | -1 | 1 | µA | VIN = 0 V or 5 V | 4 | |
| Output Logic Low (SDA) | VOL | 0.4 | V | IOL = 3 mA | 4 | ||
| Output Logic Low (SDA) | VOL | 0.6 | V | IOL = 6 mA | 4 | ||
| Power Supply Range | VDD RANGE | 2.7 | 5.5 | V | 4 | ||
| Supply Current (VDD = 5.5 V) | IDD | 3 | 7 | µA | VDD = 5.5 V; VIH = VDD or VIL = GND | 4 | |
| Supply Current (VDD = 5 V) | IDD | 2.5 | 5.2 | µA | VDD = 5 V; VIH = VDD or VIL = GND | 4 | |
| Supply Current (VDD = 3.3 V) | IDD | 0.9 | 2 | µA | VDD = 3.3 V; VIH = VDD or VIL = GND | 4 | |
| Power Dissipation | PDISS | 40 | µW | VIH = 5 V or VIL = 0 V, VDD = 5 V | 4 | ||
| Power Supply Sensitivity | PSSR | 0.01 | 0.02 | %/% | VDD = 5 V ± 10%, code = midscale | 4 | |
| Resistance Temperature Coefficient | ∆RAB/∆T | 45 | ppm/°C | 4 | |||
| Voltage Divider Temperature Coefficient | ∆VW/∆T | 15 | ppm/°C | Code = 0x40 | 4 | ||
| Capacitance A | CA | 45 | pF | f = 1 MHz, measured to GND, code = 0x40 | 4 | ||
| Capacitance W | CW | 60 | pF | f = 1 MHz, measured to GND, code = 0x40 | 4 | ||
| Input Capacitance | CIL | 5 | pF | 4 | |||
| Bandwidth -3 dB | BW | 40 | kHz | RAB = 100 kΩ, code = 0x40 | 5 | ||
| VW Settling Time (100 kΩ) | tS | 2 | µs | VA = 5 V, ±1 LSB error band | 5 | ||
| Resistor Noise Voltage Density | eN_WB | 9 | nV/√Hz | RWB = 5 kΩ, RS = 0 | 5 | ||
| SCL Clock Frequency | fSCL | 400 | kHz | 5 | |||
| Bus Free Time Between Stop and Start | tBUF | 1.3 | µs | 5 | |||
| Low Period of SCL Clock | tLOW | 1.3 | µs | 5 | |||
| High Period of SCL Clock | tHIGH | 0.6 | 50 | µs | 5 | ||
| Data Setup Time | tSU;DAT | 100 | ns | 5 | |||
| Fall Time of Both SDA and SCL Signals | tF | 300 | ns | 5 | |||
| Rise Time of Both SDA and SCL Signals | tR | 300 | ns | 5 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (Pulsed) | -20 | 20 | mA | Pulsed | 6 | ||
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (Continuous) | -5 | 5 | mA | Continuous | 6 | ||
| Operating Temperature Range | -40 | 125 | °C | 6 | |||
| Maximum Junction Temperature | TJMAX | 150 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Thermal Resistance (SC70-6) | θJA | 340 | °C/W | 6 | |||
| Nominal Resistance | RAB | 100 | kΩ | End-to-end resistance, 100 kΩ option | 1 |
CAD (KiCad official)
- Symbol:
AD5247BKSZ100-RL7 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files:
ad5247bksz100-rl7-etched.step/ad5247bksz100-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5247bksz100-rl7.step/ad5247bksz100-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
fbfe1a09b8740b04, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5247BKSZ100-RL7
**Analog Devices** · Pre-ordered Chips · SC-70-6
AD5247BKSZ100-RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply, specified for single-supply operation from 2.7 V to 5.5 V. |
| 2 | GND | power_in | Digital ground and B terminal voltage reference. |
| 3 | SCL | input | Serial clock input for the I2C-compatible interface, positive edge triggered. |
| 4 | SDA | bidirectional | Serial data input/output for the I2C-compatible interface. |
| 5 | W | passive | Terminal W, the wiper terminal of the resistor. |
| 6 | A | passive | Terminal A, one end terminal of the resistor, with no polarity limitation relative to W. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Interface ICs |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Differential Nonlinearity | R-DNL | -1 | 0.1 | 1 | LSB | RWB, VA = no connect | 4 |
| Resistor Integral Nonlinearity | R-INL | -2 | 0.25 | 2 | LSB | RWB, VA = no connect | 4 |
| Nominal Resistor Tolerance | ∆RAB | -20 | | 20 | % | VA = VDD, wiper (VW) = no connect | 4 |
| Differential Nonlinearity | DNL | -1 | 0.1 | 1 | LSB | | 4 |
| Integral Nonlinearity | INL | -1 | 0.2 | 1 | LSB | | 4 |
| Output Resistance | RWB | 75 | 300 | | Ω | RWB Code = 0x00 | 4 |
| Full-Scale Error (50 kΩ, 100 kΩ) | VWFSE | -1 | -1 | 0 | LSB | Code = 0x7F | 4 |
| Zero-Scale Error (50 kΩ, 100 kΩ) | VWZSE | 0 | 0.4 | 1 | LSB | Code = 0x00 | 4 |
| Input Logic High (VDD = 5 V) | VIH | 2.4 | | | V | VDD = 5 V | 4 |
| Input Logic Low (VDD = 5 V) | VIL | | | 0.8 | V | VDD = 5 V | 4 |
| Input Logic High (VDD = 3 V) | VIH | 2.1 | | | V | VDD = 3 V | 4 |
| Input Logic Low (VDD = 3 V) | VIL | | | 0.6 | V | VDD = 3 V | 4 |
| Input Current | IIL | -1 | | 1 | µA | VIN = 0 V or 5 V | 4 |
| Output Logic Low (SDA) | VOL | | | 0.4 | V | IOL = 3 mA | 4 |
| Output Logic Low (SDA) | VOL | | | 0.6 | V | IOL = 6 mA | 4 |
| Power Supply Range | VDD RANGE | 2.7 | | 5.5 | V | | 4 |
| Supply Current (VDD = 5.5 V) | IDD | | 3 | 7 | µA | VDD = 5.5 V; VIH = VDD or VIL = GND | 4 |
| Supply Current (VDD = 5 V) | IDD | | 2.5 | 5.2 | µA | VDD = 5 V; VIH = VDD or VIL = GND | 4 |
| Supply Current (VDD = 3.3 V) | IDD | | 0.9 | 2 | µA | VDD = 3.3 V; VIH = VDD or VIL = GND | 4 |
| Power Dissipation | PDISS | | 40 | | µW | VIH = 5 V or VIL = 0 V, VDD = 5 V | 4 |
| Power Supply Sensitivity | PSSR | | 0.01 | 0.02 | %/% | VDD = 5 V ± 10%, code = midscale | 4 |
| Resistance Temperature Coefficient | ∆RAB/∆T | | 45 | | ppm/°C | | 4 |
| Voltage Divider Temperature Coefficient | ∆VW/∆T | | 15 | | ppm/°C | Code = 0x40 | 4 |
| Capacitance A | CA | | 45 | | pF | f = 1 MHz, measured to GND, code = 0x40 | 4 |
| Capacitance W | CW | | 60 | | pF | f = 1 MHz, measured to GND, code = 0x40 | 4 |
| Input Capacitance | CIL | | 5 | | pF | | 4 |
| Bandwidth -3 dB | BW | | 40 | | kHz | RAB = 100 kΩ, code = 0x40 | 5 |
| VW Settling Time (100 kΩ) | tS | | 2 | | µs | VA = 5 V, ±1 LSB error band | 5 |
| Resistor Noise Voltage Density | eN_WB | | 9 | | nV/√Hz | RWB = 5 kΩ, RS = 0 | 5 |
| SCL Clock Frequency | fSCL | | | 400 | kHz | | 5 |
| Bus Free Time Between Stop and Start | tBUF | 1.3 | | | µs | | 5 |
| Low Period of SCL Clock | tLOW | 1.3 | | | µs | | 5 |
| High Period of SCL Clock | tHIGH | 0.6 | | 50 | µs | | 5 |
| Data Setup Time | tSU;DAT | 100 | | | ns | | 5 |
| Fall Time of Both SDA and SCL Signals | tF | | | 300 | ns | | 5 |
| Rise Time of Both SDA and SCL Signals | tR | | | 300 | ns | | 5 |
| VDD to GND | VDD | -0.3 | | 7 | V | | 6 |
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (Pulsed) | | -20 | | 20 | mA | Pulsed | 6 |
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (Continuous) | | -5 | | 5 | mA | Continuous | 6 |
| Operating Temperature Range | | -40 | | 125 | °C | | 6 |
| Maximum Junction Temperature | TJMAX | | | 150 | °C | | 6 |
| Storage Temperature Range | | -65 | | 150 | °C | | 6 |
| Thermal Resistance (SC70-6) | θJA | | 340 | | °C/W | | 6 |
| Nominal Resistance | RAB | | 100 | | kΩ | End-to-end resistance, 100 kΩ option | 1 |
## CAD (KiCad official)
- Symbol: `AD5247BKSZ100-RL7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files: `ad5247bksz100-rl7-etched.step` / `ad5247bksz100-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5247bksz100-rl7.step` / `ad5247bksz100-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5247.pdf) (20 pp, sha256 `fbfe1a09b8740b04`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5247bksz100-rl7-datasheet.pdf)