component
AD5247BKSZ10-2RL7
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5247BKSZ10-2RL7
Analog Devices · Pre-ordered Chips · SC-70-6
AD5247BKSZ10-2RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply, specified from 2.7 V to 5.5 V (Power Supply Range). |
| 2 | GND | power_in | Digital ground and B terminal voltage; the B terminal is tied to this pin. |
| 3 | SCL | input | I2C serial clock input, positive-edge triggered. |
| 4 | SDA | bidirectional | I2C serial data input/output; output logic low is 0.4 V max at IOL = 3 mA (5 V) and 0.6 V max at IOL = 6 mA. |
| 5 | W | passive | Resistor Terminal W (wiper); voltage must stay between GND and VDD, with no polarity limitation relative to Terminal A. |
| 6 | A | passive | Resistor Terminal A; voltage must stay between GND and VDD, with no polarity limitation relative to Terminal W. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Interface ICs |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Differential Nonlinearity (rheostat mode) | R-DNL | -1 | 0.1 | 1 | LSB | RWB, VA = no connect | 4 |
| Resistor Integral Nonlinearity (rheostat mode) | R-INL | -2 | 0.25 | 2 | LSB | RWB, VA = no connect | 4 |
| Nominal Resistor Tolerance | ΔRAB | -20 | 20 | % | VA = VDD, wiper (VW) = no connect | 4 | |
| Output Resistance | RWB | 75 | 300 | Ω | Code = 0x00 | 4 | |
| Differential Nonlinearity (potentiometer divider mode) | DNL | -1 | 0.1 | 1 | LSB | VA = VDD and VB = 0 V | 4 |
| Integral Nonlinearity (potentiometer divider mode) | INL | -1 | 0.2 | 1 | LSB | VA = VDD and VB = 0 V | 4 |
| Full-Scale Error (10 kΩ) | VWFSE | -2 | -0.5 | 0 | LSB | Code = 0x7F | 4 |
| Zero-Scale Error (10 kΩ) | VWZSE | 0 | 0.5 | 1 | LSB | VDD = 4.5 V to 5.5 V, code = 0x00 | 4 |
| Zero-Scale Error (10 kΩ) | VWZSE | 0 | 0.5 | 1.2 | LSB | VDD = 2.7 V to 4.4 V, code = 0x00 | 4 |
| Input Logic High | VIH | 2.4 | V | VDD = 5 V | 4 | ||
| Input Logic Low | VIL | 0.8 | V | VDD = 5 V | 4 | ||
| Input Logic High | VIH | 2.1 | V | VDD = 3 V | 4 | ||
| Input Logic Low | VIL | 0.6 | V | VDD = 3 V | 4 | ||
| Input Current | IIL | -1 | 1 | µA | VIN = 0 V or 5 V | 4 | |
| Output Logic Low (SDA) | VOL | 0.4 | V | IOL = 3 mA | 4 | ||
| Output Logic Low (SDA) | VOL | 0.6 | V | IOL = 6 mA | 4 | ||
| Power Supply Range | VDD | 2.7 | 5.5 | V | 4 | ||
| Supply Current | IDD | 3 | 7 | µA | VDD = 5.5 V; VIH = VDD or VIL = GND | 4 | |
| Supply Current | IDD | 2.5 | 5.2 | µA | VDD = 5 V; VIH = VDD or VIL = GND | 4 | |
| Supply Current | IDD | 0.9 | 2 | µA | VDD = 3.3 V; VIH = VDD or VIL = GND | 4 | |
| Power Supply Sensitivity | PSSR | -0.02 | 0.01 | 0.02 | %/% | VDD = 5 V ± 10%, code = midscale | 4 |
| SCL Clock Frequency | fSCL | 400 | kHz | 5 | |||
| Bus Free Time Between Stop and Start | t1 (tBUF) | 1.3 | µs | 5 | |||
| Hold Time (Repeated Start) | t2 (tHD;STA) | 0.6 | µs | 5 | |||
| Low Period of SCL Clock | t3 (tLOW) | 1.3 | µs | 5 | |||
| High Period of SCL Clock | t4 (tHIGH) | 0.6 | 50 | µs | 5 | ||
| Setup Time for Repeated Start Condition | t5 (tSU;STA) | 0.6 | µs | 5 | |||
| Data Hold Time | t6 (tHD;DAT) | 0.9 | µs | 5 | |||
| Data Setup Time | t7 (tSU;DAT) | 100 | ns | 5 | |||
| Fall Time of Both SDA and SCL | t8 (tF) | 300 | ns | 5 | |||
| Rise Time of Both SDA and SCL | t9 (tR) | 300 | ns | 5 | |||
| Setup Time for Stop Condition | t10 (tSU;STO) | 0.6 | µs | 5 | |||
| Total Harmonic Distortion | THDW | 0.05 | % | VA = 1 V rms, f = 1 kHz, RAB = 10 kΩ | 5 | ||
| VW Settling Time (10 kΩ) | tS | 2 | µs | VA = 5 V, ±1 LSB error band | 5 | ||
| Resistor Noise Voltage Density | eN_WB | 9 | nV/√Hz | RWB = 5 kΩ, RS = 0 | 5 | ||
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (pulsed) | -20 | 20 | mA | Pulsed | 6 | ||
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (continuous) | -5 | 5 | mA | Continuous | 6 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| Digital Inputs and Output Voltage to GND | 0 | V | to GND; max VDD + 0.3 V | 6 | |||
| Operating Temperature Range | TA | -40 | 125 | °C | 6 | ||
| Maximum Junction Temperature | TJMAX | 150 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Reflow Soldering Peak Temperature | 240 | °C | SnPb | 6 | |||
| Reflow Soldering Peak Temperature | 260 | °C | Pb-Free | 6 | |||
| Nominal End-to-End Resistance | RAB | 10 | kΩ | 10 kΩ version | 14 | ||
| Resistance Temperature Coefficient | ΔRAB/ΔT | 45 | ppm/°C | 4 | |||
| Voltage Divider Temperature Coefficient | ΔVW/ΔT | 15 | ppm/°C | Code = 0x40 | 4 | ||
| Thermal Resistance, Junction-to-Ambient (SC70-6) | θJA | 340 | °C/W | SC70-6 package | 6 |
CAD (KiCad official)
- Symbol:
AD5247BKSZ10-2RL7 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files:
ad5247bksz10-2rl7-etched.step/ad5247bksz10-2rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5247bksz10-2rl7.step/ad5247bksz10-2rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
fbfe1a09b8740b04, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5247BKSZ10-2RL7
**Analog Devices** · Pre-ordered Chips · SC-70-6
AD5247BKSZ10-2RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply, specified from 2.7 V to 5.5 V (Power Supply Range). |
| 2 | GND | power_in | Digital ground and B terminal voltage; the B terminal is tied to this pin. |
| 3 | SCL | input | I2C serial clock input, positive-edge triggered. |
| 4 | SDA | bidirectional | I2C serial data input/output; output logic low is 0.4 V max at IOL = 3 mA (5 V) and 0.6 V max at IOL = 6 mA. |
| 5 | W | passive | Resistor Terminal W (wiper); voltage must stay between GND and VDD, with no polarity limitation relative to Terminal A. |
| 6 | A | passive | Resistor Terminal A; voltage must stay between GND and VDD, with no polarity limitation relative to Terminal W. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Interface ICs |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Differential Nonlinearity (rheostat mode) | R-DNL | -1 | 0.1 | 1 | LSB | RWB, VA = no connect | 4 |
| Resistor Integral Nonlinearity (rheostat mode) | R-INL | -2 | 0.25 | 2 | LSB | RWB, VA = no connect | 4 |
| Nominal Resistor Tolerance | ΔRAB | -20 | | 20 | % | VA = VDD, wiper (VW) = no connect | 4 |
| Output Resistance | RWB | | 75 | 300 | Ω | Code = 0x00 | 4 |
| Differential Nonlinearity (potentiometer divider mode) | DNL | -1 | 0.1 | 1 | LSB | VA = VDD and VB = 0 V | 4 |
| Integral Nonlinearity (potentiometer divider mode) | INL | -1 | 0.2 | 1 | LSB | VA = VDD and VB = 0 V | 4 |
| Full-Scale Error (10 kΩ) | VWFSE | -2 | -0.5 | 0 | LSB | Code = 0x7F | 4 |
| Zero-Scale Error (10 kΩ) | VWZSE | 0 | 0.5 | 1 | LSB | VDD = 4.5 V to 5.5 V, code = 0x00 | 4 |
| Zero-Scale Error (10 kΩ) | VWZSE | 0 | 0.5 | 1.2 | LSB | VDD = 2.7 V to 4.4 V, code = 0x00 | 4 |
| Input Logic High | VIH | 2.4 | | | V | VDD = 5 V | 4 |
| Input Logic Low | VIL | | | 0.8 | V | VDD = 5 V | 4 |
| Input Logic High | VIH | 2.1 | | | V | VDD = 3 V | 4 |
| Input Logic Low | VIL | | | 0.6 | V | VDD = 3 V | 4 |
| Input Current | IIL | -1 | | 1 | µA | VIN = 0 V or 5 V | 4 |
| Output Logic Low (SDA) | VOL | | | 0.4 | V | IOL = 3 mA | 4 |
| Output Logic Low (SDA) | VOL | | | 0.6 | V | IOL = 6 mA | 4 |
| Power Supply Range | VDD | 2.7 | | 5.5 | V | | 4 |
| Supply Current | IDD | | 3 | 7 | µA | VDD = 5.5 V; VIH = VDD or VIL = GND | 4 |
| Supply Current | IDD | | 2.5 | 5.2 | µA | VDD = 5 V; VIH = VDD or VIL = GND | 4 |
| Supply Current | IDD | | 0.9 | 2 | µA | VDD = 3.3 V; VIH = VDD or VIL = GND | 4 |
| Power Supply Sensitivity | PSSR | -0.02 | 0.01 | 0.02 | %/% | VDD = 5 V ± 10%, code = midscale | 4 |
| SCL Clock Frequency | fSCL | | | 400 | kHz | | 5 |
| Bus Free Time Between Stop and Start | t1 (tBUF) | 1.3 | | | µs | | 5 |
| Hold Time (Repeated Start) | t2 (tHD;STA) | 0.6 | | | µs | | 5 |
| Low Period of SCL Clock | t3 (tLOW) | 1.3 | | | µs | | 5 |
| High Period of SCL Clock | t4 (tHIGH) | 0.6 | | 50 | µs | | 5 |
| Setup Time for Repeated Start Condition | t5 (tSU;STA) | 0.6 | | | µs | | 5 |
| Data Hold Time | t6 (tHD;DAT) | 0.9 | | | µs | | 5 |
| Data Setup Time | t7 (tSU;DAT) | 100 | | | ns | | 5 |
| Fall Time of Both SDA and SCL | t8 (tF) | | | 300 | ns | | 5 |
| Rise Time of Both SDA and SCL | t9 (tR) | | | 300 | ns | | 5 |
| Setup Time for Stop Condition | t10 (tSU;STO) | 0.6 | | | µs | | 5 |
| Total Harmonic Distortion | THDW | | | 0.05 | % | VA = 1 V rms, f = 1 kHz, RAB = 10 kΩ | 5 |
| VW Settling Time (10 kΩ) | tS | | | 2 | µs | VA = 5 V, ±1 LSB error band | 5 |
| Resistor Noise Voltage Density | eN_WB | | 9 | | nV/√Hz | RWB = 5 kΩ, RS = 0 | 5 |
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (pulsed) | | -20 | | 20 | mA | Pulsed | 6 |
| Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx (continuous) | | -5 | | 5 | mA | Continuous | 6 |
| VDD to GND | VDD | -0.3 | | 7 | V | | 6 |
| Digital Inputs and Output Voltage to GND | | 0 | | | V | to GND; max VDD + 0.3 V | 6 |
| Operating Temperature Range | TA | -40 | | 125 | °C | | 6 |
| Maximum Junction Temperature | TJMAX | | | 150 | °C | | 6 |
| Storage Temperature Range | | -65 | | 150 | °C | | 6 |
| Reflow Soldering Peak Temperature | | | | 240 | °C | SnPb | 6 |
| Reflow Soldering Peak Temperature | | | | 260 | °C | Pb-Free | 6 |
| Nominal End-to-End Resistance | RAB | | 10 | | kΩ | 10 kΩ version | 14 |
| Resistance Temperature Coefficient | ΔRAB/ΔT | | 45 | | ppm/°C | | 4 |
| Voltage Divider Temperature Coefficient | ΔVW/ΔT | | 15 | | ppm/°C | Code = 0x40 | 4 |
| Thermal Resistance, Junction-to-Ambient (SC70-6) | θJA | | 340 | | °C/W | SC70-6 package | 6 |
## CAD (KiCad official)
- Symbol: `AD5247BKSZ10-2RL7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files: `ad5247bksz10-2rl7-etched.step` / `ad5247bksz10-2rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5247bksz10-2rl7.step` / `ad5247bksz10-2rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5247.pdf) (20 pp, sha256 `fbfe1a09b8740b04`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5247bksz10-2rl7-datasheet.pdf)