component
AD5246BKSZ5-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5246BKSZ5-RL7
Analog Devices · Digital Potentiometers · SC-70-6
AD5246BKSZ5-RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply, specified from 2.7 V to 5.5 V, with absolute maximum VDD to GND of −0.3 V to +7 V. |
| 2 | GND | power_in | Digital ground, which should be joined remotely to the analog ground at one point to minimize ground bounce. |
| 3 | SCL | input | Serial clock input, positive edge triggered, with VIH of 2.4 V minimum and VIL of 0.8 V maximum at VDD = 5 V. |
| 4 | SDA | bidirectional | Serial data input/output for the I2C interface, with VIH of 2.4 V minimum and VIL of 0.8 V maximum at VDD = 5 V. |
| 5 | W | passive | Wiper terminal of the RDAC, which may be at any voltage between GND and VDD, with continuous terminal current limited to ±5 mA and pulsed current to ±20 mA. |
| 6 | B | passive | B terminal of the RDAC, which may be at any voltage between GND and VDD, with continuous terminal current limited to ±5 mA and pulsed current to ±20 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Data Converters |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal Resistor Tolerance | ∆RAB | -30 | 30 | % | TA = 25°C | 3 | |
| Resistor Differential Nonlinearity | R-DNL | -1.5 | 0.1 | 1.5 | LSB | RWB | 3 |
| Resistor Integral Nonlinearity | R-INL | -4 | 0.75 | 4 | LSB | RWB | 3 |
| RWB | RWB | 75 | 150 | Ω | Code = 0x00, VDD = 5 V | 3 | |
| RWB | RWB | 150 | 400 | Ω | Code = 0x00, VDD = 2.7 V | 3 | |
| Power Supply Range | VDD RANGE | 2.7 | 5.5 | V | 3 | ||
| Input Logic High | VIH | 2.4 | V | VDD = 5 V | 3 | ||
| Input Logic Low | VIL | 0.8 | V | VDD = 5 V | 3 | ||
| Input Logic High | VIH | 2.1 | V | VDD = 3 V | 3 | ||
| Input Logic Low | VIL | 0.6 | V | VDD = 3 V | 3 | ||
| Input Current | IIL | -1 | 1 | µA | VIN = 0 V or 5 V | 3 | |
| Supply Current | IDD | 3 | 7 | µA | VDD = 5.5 V; VIH = VDD or VIL = GND | 3 | |
| Supply Current | IDD | 2.5 | 5.2 | µA | VDD = 5 V; VIH = VDD or VIL = GND | 3 | |
| Supply Current | IDD | 0.9 | 2 | µA | VDD = 3.3 V; VIH = VDD or VIL = GND | 3 | |
| Power Supply Sensitivity | PSSR | -0.025 | 0.01 | 0.025 | %/% | VDD = +5 V ± 10%, code = midscale | 3 |
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| Terminal Current, A-B, A-W, B-W | -20 | 20 | mA | Pulsed | 6 | ||
| Terminal Current, A-B, A-W, B-W | -5 | 5 | mA | Continuous | 6 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | 6 | ||
| Maximum Junction Temperature | TJMAX | 150 | °C | 6 | |||
| Storage Temperature | -65 | 150 | °C | 6 | |||
| Lead Temperature (Soldering) | 300 | °C | Soldering, 10 sec | 6 | |||
| SCL Clock Frequency | fSCL | 400 | kHz | 5 | |||
| Bus Free Time Between STOP and START | t1 | 1.3 | µs | 5 | |||
| Low Period of SCL Clock | t3 | 1.3 | µs | 5 | |||
| High Period of SCL Clock | t4 | 0.6 | 50 | µs | 5 | ||
| Hold Time (Repeated START) | t2 | 0.6 | µs | After this period, the first clock pulse is generated | 5 | ||
| Setup Time for Repeated START Condition | t5 | 0.6 | µs | 5 | |||
| Data Hold Time | t6 | 0.9 | µs | 5 | |||
| Data Setup Time | t7 | 100 | ns | 5 | |||
| Fall Time of Both SDA and SCL Signals | t8 | 300 | ns | 5 | |||
| Rise Time of Both SDA and SCL Signals | t9 | 300 | ns | 5 | |||
| Setup Time for STOP Condition | t10 | 0.6 | µs | 5 | |||
| End-to-end Resistance (nominal) | RAB | 5 | kΩ | Ordering guide: AD5246BKSZ5-RL7 RAB 5 kΩ | 16 | ||
| Resistance Temperature Coefficient | (∆RAB/RAB)/∆T | 45 | ppm/°C | Wiper = no connect | 3 | ||
| Thermal Resistance θJA | θJA | 340 | °C/W | SC70-6 | 6 |
CAD (KiCad official)
- Symbol:
AD5246BKSZ5-RL7 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files:
ad5246bksz5-rl7-etched.step/ad5246bksz5-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5246bksz5-rl7.step/ad5246bksz5-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
fb96c0088bd35992, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5246BKSZ5-RL7
**Analog Devices** · Digital Potentiometers · SC-70-6
AD5246BKSZ5-RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive power supply, specified from 2.7 V to 5.5 V, with absolute maximum VDD to GND of −0.3 V to +7 V. |
| 2 | GND | power_in | Digital ground, which should be joined remotely to the analog ground at one point to minimize ground bounce. |
| 3 | SCL | input | Serial clock input, positive edge triggered, with VIH of 2.4 V minimum and VIL of 0.8 V maximum at VDD = 5 V. |
| 4 | SDA | bidirectional | Serial data input/output for the I2C interface, with VIH of 2.4 V minimum and VIL of 0.8 V maximum at VDD = 5 V. |
| 5 | W | passive | Wiper terminal of the RDAC, which may be at any voltage between GND and VDD, with continuous terminal current limited to ±5 mA and pulsed current to ±20 mA. |
| 6 | B | passive | B terminal of the RDAC, which may be at any voltage between GND and VDD, with continuous terminal current limited to ±5 mA and pulsed current to ±20 mA. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Data Converters |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Nominal Resistor Tolerance | ∆RAB | -30 | | 30 | % | TA = 25°C | 3 |
| Resistor Differential Nonlinearity | R-DNL | -1.5 | 0.1 | 1.5 | LSB | RWB | 3 |
| Resistor Integral Nonlinearity | R-INL | -4 | 0.75 | 4 | LSB | RWB | 3 |
| RWB | RWB | | 75 | 150 | Ω | Code = 0x00, VDD = 5 V | 3 |
| RWB | RWB | | 150 | 400 | Ω | Code = 0x00, VDD = 2.7 V | 3 |
| Power Supply Range | VDD RANGE | 2.7 | | 5.5 | V | | 3 |
| Input Logic High | VIH | 2.4 | | | V | VDD = 5 V | 3 |
| Input Logic Low | VIL | | | 0.8 | V | VDD = 5 V | 3 |
| Input Logic High | VIH | 2.1 | | | V | VDD = 3 V | 3 |
| Input Logic Low | VIL | | | 0.6 | V | VDD = 3 V | 3 |
| Input Current | IIL | -1 | | 1 | µA | VIN = 0 V or 5 V | 3 |
| Supply Current | IDD | | 3 | 7 | µA | VDD = 5.5 V; VIH = VDD or VIL = GND | 3 |
| Supply Current | IDD | | 2.5 | 5.2 | µA | VDD = 5 V; VIH = VDD or VIL = GND | 3 |
| Supply Current | IDD | | 0.9 | 2 | µA | VDD = 3.3 V; VIH = VDD or VIL = GND | 3 |
| Power Supply Sensitivity | PSSR | -0.025 | 0.01 | 0.025 | %/% | VDD = +5 V ± 10%, code = midscale | 3 |
| VDD to GND | VDD | -0.3 | | 7 | V | | 6 |
| Terminal Current, A-B, A-W, B-W | | -20 | | 20 | mA | Pulsed | 6 |
| Terminal Current, A-B, A-W, B-W | | -5 | | 5 | mA | Continuous | 6 |
| Operating Temperature Range | TA | -40 | | 125 | °C | | 6 |
| Maximum Junction Temperature | TJMAX | | | 150 | °C | | 6 |
| Storage Temperature | | -65 | | 150 | °C | | 6 |
| Lead Temperature (Soldering) | | | | 300 | °C | Soldering, 10 sec | 6 |
| SCL Clock Frequency | fSCL | | | 400 | kHz | | 5 |
| Bus Free Time Between STOP and START | t1 | 1.3 | | | µs | | 5 |
| Low Period of SCL Clock | t3 | 1.3 | | | µs | | 5 |
| High Period of SCL Clock | t4 | 0.6 | | 50 | µs | | 5 |
| Hold Time (Repeated START) | t2 | 0.6 | | | µs | After this period, the first clock pulse is generated | 5 |
| Setup Time for Repeated START Condition | t5 | 0.6 | | | µs | | 5 |
| Data Hold Time | t6 | 0.9 | | | µs | | 5 |
| Data Setup Time | t7 | 100 | | | ns | | 5 |
| Fall Time of Both SDA and SCL Signals | t8 | | | 300 | ns | | 5 |
| Rise Time of Both SDA and SCL Signals | t9 | | | 300 | ns | | 5 |
| Setup Time for STOP Condition | t10 | 0.6 | | | µs | | 5 |
| End-to-end Resistance (nominal) | RAB | | 5 | | kΩ | Ordering guide: AD5246BKSZ5-RL7 RAB 5 kΩ | 16 |
| Resistance Temperature Coefficient | (∆RAB/RAB)/∆T | | 45 | | ppm/°C | Wiper = no connect | 3 |
| Thermal Resistance θJA | θJA | | 340 | | °C/W | SC70-6 | 6 |
## CAD (KiCad official)
- Symbol: `AD5246BKSZ5-RL7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files: `ad5246bksz5-rl7-etched.step` / `ad5246bksz5-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5246bksz5-rl7.step` / `ad5246bksz5-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5246.pdf) (16 pp, sha256 `fb96c0088bd35992`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5246bksz5-rl7-datasheet.pdf)