AD5242BRZ100 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	O1	output	Logic Output Terminal O1 is a push-pull output that equals VDD or VSS and can drive milliamperes of load.
2	A1	passive	Resistor Terminal A1 of the first variable resistor channel.
3	W1	passive	Wiper Terminal W1 of the first variable resistor channel.
4	B1	passive	Resistor Terminal B1 of the first variable resistor channel.
5	VDD	power_in	Positive Power Supply, specified for operation from 2.2 V to 5.5 V.
6	SHDN	input	Active-low asynchronous shutdown that connects wiper W to terminal B and opens terminal A, leaving RDAC register contents unchanged; tie to VDD if not used.
7	SCL	input	Serial Clock Input for the I2C-compatible interface.
8	SDA	bidirectional	Serial Data Input/Output for the I2C-compatible interface.
9	AD0	input	Programmable address bit for multiple-package decoding; bits AD0 and AD1 provide four possible addresses.
10	AD1	input	Programmable address bit for multiple-package decoding; bits AD0 and AD1 provide four possible addresses.
11	DGND	power_in	Common ground for the digital circuitry.
12	VSS	power_in	Negative Power Supply, specified for operation from 0 V to −2.7 V.
13	O2	output	Logic Output Terminal O2 is a push-pull output that equals VDD or VSS and can drive milliamperes of load.
14	B2	passive	Resistor Terminal B2 of the second variable resistor channel.
15	W2	passive	Wiper Terminal W2 of the second variable resistor channel.
16	A2	passive	Resistor Terminal A2 of the second variable resistor channel.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-16
Category	Data Converters
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Nominal resistor tolerance (RAB = 100 kΩ/1 MΩ)	ΔRAB/RAB	-30		50	%	TA = 25°C, RAB = 100 kΩ/1 MΩ	3
Resistor differential nonlinearity	R-DNL	-1	0.4	1	LSB	RWB, VA = no connect	3
Resistor integral nonlinearity	R-INL	-2	0.5	2	LSB	RWB, VA = no connect	3
Differential nonlinearity	DNL	-1	0.4	1	LSB		3
Integral nonlinearity	INL	-2	0.5	2	LSB		3
Full-scale error	VWFSE	-1	-0.5	0	LSB	Code = 0xFF	3
Zero-scale error	VWZSE	0	0.5	1	LSB	Code = 0x00	3
Wiper resistance	RW		60	120	Ω	IW = VDD/R	3
Common-mode leakage	ICM			1	nA	VA = VB = VW	3
Input logic low (SDA and SCL)	VIL	-0.5			V		3
Input logic high (AD0 and AD1), VDD = 5 V	VIH	2.4			V	VDD = 5 V	3
Input logic low (AD0 and AD1), VDD = 5 V	VIL	0		0.8	V	VDD = 5 V	3
Input logic high, VDD = 3 V	VIH	2.1			V	VDD = 3 V	3
Input logic low, VDD = 3 V	VIL	0		0.6	V	VDD = 3 V	3
Input current	IIL			1	µA	VIH = 5 V or VIL = GND	3
Digital output logic low	VOL			0.4	V	IOL = 3 mA	3
Output logic low (SDA)	VOL			0.6	V	IOL = 6 mA	3
Output logic low (O1 and O2)	VOL			0.4	V	ISINK = 1.6 mA	3
Output logic high (O1 and O2)	VOH	4			V	ISOURCE = 40 µA	3
Three-state leakage current (SDA)	IOZ	-1		1	µA	VIH = 5 V or VIL = GND	3
Output capacitance	COZ		3	8	pF		3
Power single-supply range	VDD	2.7		5.5	V	VSS = 0 V	3
Power dual-supply range	VDD/VSS	2.3		2.7	V		3
Positive supply current	IDD		0.1	50	µA	VIH = 5 V or VIL = GND	3
Negative supply current	ISS		0.1	-50	µA	VSS = −2.5 V, VDD = +2.5 V	3
Power dissipation	PDISS		0.5	250	µW	VIH = 5 V or VIL = GND, VDD = 5 V	3
Power supply sensitivity	PSS	-0.01	0.002	0.01	%/%		3
SCL clock frequency	fSCL	0		400	kHz		4
Bus free time between stop and start	tBUF	1.3			µs		4
Hold time (repeated start)	tHD; STA	600			ns	After this period, the first clock pulse is generated	4
Low period of SCL clock	tLOW	1.3			µs		4
High period of SCL clock	tHIGH	0.6		50	µs		4
Setup time for repeated start condition	tSU; STA	600			ns		4
Data hold time	tHD; DAT	900			ns		4
Data setup time	tSU; DAT	100			ns		4
Rise time of both SDA and SCL	tR			300	ns		4
Fall time of both SDA and SCL	tF			300	ns		4
Setup time for stop condition	tSU; STO	0.6			µs		4
VDD to GND	VDD	-0.3		7	V		6
VSS to GND	VSS	-7		0	V		6
VDD to VSS	VDD to VSS			7	V		6
Digital input voltage to GND	VIN	0			V		6
Operating temperature range	TA	-40		105	°C		6
Storage temperature range	TSTG	-65		150	°C		6
Maximum junction temperature	TJ max			150	°C		6
Lead temperature, vapor phase				215	°C	Vapor phase, 60 sec	6
Lead temperature, infrared				220	°C	Infrared, 15 sec	6
Nominal end-to-end resistance	RAB		100		kΩ		12
Resistance temperature coefficient	(ΔRAB/RAB)/ΔT × 10^6		30		ppm/°C	VAB = VDD, wiper = no connect	3
Voltage divider temperature coefficient	(ΔVW/VW)/ΔT × 10^6		5		ppm/°C	Code = 0x80	3
Capacitance (A, B)	CA, CB		45		pF	f = 1 MHz, measured to GND, code = 0x80	3
Capacitance (W)	CW		60		pF	f = 1 MHz, measured to GND, code = 0x80	3
Input capacitance	CIL		3		pF		3
−3 dB bandwidth (100 kΩ)	BW_100 kΩ		69		kHz	RAB = 100 kΩ, code = 0x80	3
Total harmonic distortion	THDW		0.005		%	VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz	3
Resistor noise voltage	eN_WB		14		nV√Hz	RWB = 5 kΩ, f = 1 kHz	3
Thermal resistance, junction-to-ambient, 16-lead SOIC	θJA		73		°C/W		6

CAD (KiCad official)

Symbol: AD5242BRZ100
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: ad5242brz100-etched.step / ad5242brz100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5242brz100.step / ad5242brz100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (17 pp, sha256 b10cb8d6bde9cac7, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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AD5242BRZ100

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