component
AD5242BRUZ10-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD5242BRUZ10-RL7
Analog Devices · Digital Potentiometers · TSSOP-16
AD5242BRUZ10-RL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | O1 | output | Logic output terminal O1 that drives digital loads, logic gates, LED drivers, or analog switches, and defaults to Logic 0 at power-up. |
| 2 | A1 | passive | Resistor Terminal A1 of the first variable resistor channel. |
| 3 | W1 | passive | Wiper Terminal W1 of the first variable resistor channel. |
| 4 | B1 | passive | Resistor Terminal B1 of the first variable resistor channel. |
| 5 | VDD | power_in | Positive power supply, specified for operation from 2.2 V to 5.5 V. |
| 6 | SHDN | input | Active low asynchronous shutdown that connects Wiper W to Terminal B and open-circuits Terminal A, with RDAC register contents unchanged; it should tie to VDD if not used. |
| 7 | SCL | input | Serial clock input for the I2C-compatible serial interface. |
| 8 | SDA | bidirectional | Serial data input/output for the I2C-compatible serial interface. |
| 9 | AD0 | input | Programmable package address bit; bit AD0 and bit AD1 provide four possible device addresses. |
| 10 | AD1 | input | Programmable package address bit; bit AD0 and bit AD1 provide four possible device addresses. |
| 11 | DGND | power_in | Common ground. |
| 12 | VSS | power_in | Negative power supply, specified for operation from 0 V to −2.7 V. |
| 13 | O2 | output | Logic output terminal O2 that drives digital loads, logic gates, LED drivers, or analog switches. |
| 14 | B2 | passive | Resistor Terminal B2 of the second variable resistor channel. |
| 15 | W2 | passive | Wiper Terminal W2 of the second variable resistor channel. |
| 16 | A2 | passive | Resistor Terminal A2 of the second variable resistor channel. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Differential Nonlinearity | R-DNL | -1 | 0.4 | 1 | LSB | RWB, VA = no connect | 3 |
| Resistor Integral Nonlinearity | R-INL | -2 | 0.5 | 2 | LSB | RWB, VA = no connect | 3 |
| Nominal Resistor Tolerance (10 kΩ, nominal value 10 kΩ) | ΔRAB/RAB | -30 | 30 | % | TA = 25°C, RAB = 10 kΩ | 3 | |
| Nominal resistance (RAB) | RAB | 10 | kΩ | 10 kΩ variant (ordering suffix 10) | 3 | ||
| Resistance Temperature Coefficient | (ΔRAB/RAB)/ΔT × 10^6 | 30 | ppm/°C | VAB = VDD, wiper = no connect | 3 | ||
| Wiper Resistance | RW | 60 | 120 | Ω | IW = VDD/R | 3 | |
| Voltage Divider Temperature Coefficient | (ΔVW/VW)/ΔT × 10^6 | 5 | ppm/°C | Code = 0x80 | 3 | ||
| Differential Nonlinearity (potentiometer divider) | DNL | -1 | 0.4 | 1 | LSB | 3 | |
| Integral Nonlinearity (potentiometer divider) | INL | -2 | 0.5 | 2 | LSB | 3 | |
| Full-Scale Error | VWFSE | -1 | -0.5 | 0 | LSB | Code = 0xFF | 3 |
| Zero-Scale Error | VWZSE | 0 | 0.5 | 1 | LSB | Code = 0x00 | 3 |
| Capacitance (A, B) | CA, CB | 45 | pF | f = 1 MHz, measured to GND, code = 0x80 | 3 | ||
| Capacitance (W) | CW | 60 | pF | f = 1 MHz, measured to GND, code = 0x80 | 3 | ||
| Common-Mode Leakage | ICM | 1 | nA | VA = VB = VW | 3 | ||
| Input Logic Low (AD0 and AD1) | VIL | 0 | 0.8 | V | VDD = 5 V | 3 | |
| Input Logic High (AD0 and AD1) | VIH | 2.4 | V | VDD = 5 V | 3 | ||
| Input Logic High | VIH | 2.1 | V | VDD = 3 V | 3 | ||
| Input Logic Low | VIL | 0 | 0.6 | V | VDD = 3 V | 3 | |
| Input Current | IIL | 1 | µA | VIH = 5 V or VIL = GND | 3 | ||
| Input Capacitance | CIL | 3 | pF | 3 | |||
| Output Logic Low (SDA) | VOL | 0.4 | V | IOL = 3 mA | 3 | ||
| Output Logic Low (SDA) | VOL | 0.6 | V | IOL = 6 mA | 3 | ||
| Output Logic Low (O1 and O2) | VOL | 0.4 | V | ISINK = 1.6 mA | 3 | ||
| Output Logic High (O1 and O2) | VOH | 4 | V | ISOURCE = 40 µA | 3 | ||
| Three-State Leakage Current (SDA) | IOZ | -1 | 1 | µA | VIH = 5 V or VIL = GND | 3 | |
| Output Capacitance | COZ | 3 | 8 | pF | 3 | ||
| Power Single-Supply Range | VDD | 2.7 | 5.5 | V | VSS = 0 V | 3 | |
| Positive Supply Current | IDD | 0.1 | 50 | µA | VIH = 5 V or VIL = GND | 3 | |
| Negative Supply Current | ISS | 0.1 | -50 | µA | VSS = -2.5 V, VDD = +2.5 V | 3 | |
| Power Dissipation | PDISS | 0.5 | 250 | µW | VIH = 5 V or VIL = GND, VDD = 5 V | 3 | |
| Power Supply Sensitivity | PSS | -0.01 | 0.002 | 0.01 | %/% | 3 | |
| -3 dB Bandwidth (10 kΩ) | BW_10 kΩ | 650 | kHz | RAB = 10 kΩ, code = 0x80 | 3 | ||
| Total Harmonic Distortion | THDW | 0.005 | % | VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz | 3 | ||
| VW Settling Time | tS | 2 | µs | VA = VDD, VB = 0 V, ±1 LSB error band, RAB = 10 kΩ | 3 | ||
| Resistor Noise Voltage | eN_WB | 14 | nV√Hz | RWB = 5 kΩ, f = 1 kHz | 3 | ||
| SCL Clock Frequency | fSCL | 0 | 400 | kHz | 4 | ||
| Bus Free Time Between Stop and Start | tBUF | 1.3 | µs | 4 | |||
| Hold Time (Repeated Start) | tHD; STA | 600 | ns | After this period, the first clock pulse is generated | 4 | ||
| Low Period of SCL Clock | tLOW | 1.3 | µs | 4 | |||
| High Period of SCL Clock | tHIGH | 0.6 | 50 | µs | 4 | ||
| Setup Time for Repeated Start Condition | tSU; STA | 600 | ns | 4 | |||
| Data Hold Time | tHD; DAT | 900 | ns | 4 | |||
| Data Setup Time | tSU; DAT | 100 | ns | 4 | |||
| Rise Time of Both SDA and SCL Signals | tR | 300 | ns | 4 | |||
| Fall Time of Both SDA and SCL Signals | tF | 300 | ns | 4 | |||
| Setup Time for Stop Condition | tSU; STO | 0.6 | µs | 4 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| VSS to GND | VSS | -7 | 0 | V | 6 | ||
| VDD to VSS | VDD-VSS | 7 | V | 6 | |||
| Digital Input Voltage to GND | 0 | V | Max is VDD + 0.3 V as printed | 6 | |||
| Operating Temperature Range | TA | -40 | 105 | °C | 6 | ||
| Thermal Resistance θJA, 16-Lead TSSOP | θJA | 180 | °C/W | 16-Lead TSSOP | 6 | ||
| Maximum Junction Temperature | TJ max | 150 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Lead Temperature, Vapor Phase | 215 | °C | 60 sec | 6 | |||
| Lead Temperature, Infrared | 220 | °C | 15 sec | 6 |
CAD (KiCad official)
- Symbol:
AD5242BRUZ10-RL7 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad5242bruz10-rl7-etched.step/ad5242bruz10-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5242bruz10-rl7.step/ad5242bruz10-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (17 pp, sha256
b10cb8d6bde9cac7, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).