AD5144BRUZ100 from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SYNC	input	Active-low synchronization data input; when SYNC returns high, data is loaded into the input shift register.
2	GND	power_in	Logic ground reference pin.
3	A1	passive	Terminal A of RDAC1; VSS ≤ VA ≤ VDD.
4	W1	passive	Wiper terminal of RDAC1; VSS ≤ VW ≤ VDD.
5	B1	passive	Terminal B of RDAC1; VSS ≤ VB ≤ VDD.
6	A3	passive	Terminal A of RDAC3; VSS ≤ VA ≤ VDD.
7	W3	passive	Wiper terminal of RDAC3; VSS ≤ VW ≤ VDD.
8	B3	passive	Terminal B of RDAC3; VSS ≤ VB ≤ VDD.
9	VSS	power_in	Negative power supply; decouple with 0.1 µF ceramic capacitors and 10 µF capacitors.
10	A2	passive	Terminal A of RDAC2; VSS ≤ VA ≤ VDD.
11	W2	passive	Wiper terminal of RDAC2; VSS ≤ VW ≤ VDD.
12	B2	passive	Terminal B of RDAC2; VSS ≤ VB ≤ VDD.
13	A4	passive	Terminal A of RDAC4; VSS ≤ VA ≤ VDD.
14	W4	passive	Wiper terminal of RDAC4; VSS ≤ VW ≤ VDD.
15	B4	passive	Terminal B of RDAC4; VSS ≤ VB ≤ VDD.
16	VDD	power_in	Positive power supply; decouple with 0.1 µF ceramic capacitors and 10 µF capacitors.
17	VLOGIC	power_in	Logic power supply, 1.8 V to VDD; decouple with 0.1 µF ceramic capacitors and 10 µF capacitors.
18	SCLK	input	Serial clock line; data is clocked in at the logic low transition.
19	SDI	input	Serial data input.
20	SDO	output	Open-drain serial data output that requires an external pull-up resistor.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-20
Category	ADC/DAC/Data Conversion
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Resistor Integral Nonlinearity, VDD ≥ 2.7 V	R-INL	-1	0.1	1	LSB	RAB = 100 kΩ, VDD ≥ 2.7 V	7
Resistor Integral Nonlinearity, VDD < 2.7 V	R-INL	-2	0.5	2	LSB	RAB = 100 kΩ, VDD < 2.7 V	7
Resistor Integral Nonlinearity, VDD ≥ 2.7 V	R-INL	-2	0.2	2	LSB	RAB = 10 kΩ, VDD ≥ 2.7 V	7
Resistor Integral Nonlinearity, VDD < 2.7 V	R-INL	-5	1.5	5	LSB	RAB = 10 kΩ, VDD < 2.7 V	7
Resistor Differential Nonlinearity	R-DNL	-0.5	0.2	0.5	LSB		7
Nominal Resistor Tolerance	ΔRAB/RAB	-8	1	8	%		7
Nominal Resistance Match	RAB1/RAB2	-1	0.2	1	%	Code = full scale	7
Integral Nonlinearity, potentiometer divider	INL	-1	0.2	1	LSB	RAB = 10 kΩ	7
Integral Nonlinearity, potentiometer divider	INL	-0.5	0.1	0.5	LSB	RAB = 100 kΩ	7
Differential Nonlinearity, potentiometer divider	DNL	-0.5	0.2	0.5	LSB		7
Full-Scale Error	VWFSE	-2.5		-0.1	LSB	RAB = 10 kΩ	7
Full-Scale Error	VWFSE	-1	0.2	1	LSB	RAB = 100 kΩ	7
Zero-Scale Error	VWZSE		1.2	3	LSB	RAB = 10 kΩ	7
Zero-Scale Error	VWZSE		0.5	1	LSB	RAB = 100 kΩ	7
Voltage Divider Temperature Coefficient	(ΔVW/VW)/ΔT × 10^6	-5		5	ppm/°C	Code = half scale	7
Maximum Continuous Current, IA, IB, IW	IA, IB, IW	-6		6	mA	RAB = 10 kΩ	7
Common-Mode Leakage Current		-500	15	500	nA	VA = VW = VB	8
Input Current	IIN	-1		1	µA		8
Output Low Voltage	VOL			0.4	V	ISINK = 3 mA	8
Output Low Voltage	VOL			0.6	V	ISINK = 6 mA, VLOGIC > 2.3 V	8
Three-State Leakage Current		-1		1	µA		8
Single-Supply Power Range	VDD	2.3		5.5	V	VSS = GND	8
Dual-Supply Power Range	VDD/VSS	2.25		2.75	V		8
Logic Supply Range, single supply	VLOGIC	1.8			V	Single supply, VSS = GND	8
Logic Supply Range, dual supply	VLOGIC	2.25			V	Dual supply, VSS < GND	8
Positive Supply Current	IDD		0.7	5.5	µA	VIH = VLOGIC or VIL = GND; VDD = 5.5 V	8
Positive Supply Current	IDD			400	nA	VIH = VLOGIC or VIL = GND; VDD = 2.3 V	8
Negative Supply Current	ISS	-5.5		-0.7	µA	VIH = VLOGIC or VIL = GND	8
EEPROM Store Current	IDD_EEPROM_STORE			2	mA	VIH = VLOGIC or VIL = GND	8
EEPROM Read Current	IDD_EEPROM_READ			320	µA	VIH = VLOGIC or VIL = GND	8
Logic Supply Current	ILOGIC		0.05	1.4	µA	VIH = VLOGIC or VIL = GND	8
Power Supply Rejection Ratio	PSRR	-66		-60	dB	ΔVDD/ΔVSS = VDD ± 10%, code = full scale	8
Endurance		1			Mcycles	TA = 25°C	8
Endurance		100			kcycles		9
Data Retention		50			Years		9
VDD to GND	VDD	-0.3		7	V		14
VSS to GND	VSS	-7		0.3	V		14
VDD to VSS	VDD-VSS			7	V		14
VLOGIC to GND	VLOGIC	-0.3			V	VDD + 0.3 V or +7.0 V, whichever is less	14
Pulsed terminal current IA, IW, IB, RAB = 10 kΩ, frequency > 10 kHz	IA, IW, IB	-6		6	mA/d	RAB = 10 kΩ, frequency > 10 kHz, d = pulse duty factor	14
Pulsed terminal current IA, IW, IB, RAB = 100 kΩ, frequency > 10 kHz	IA, IW, IB	-1.5		1.5	mA/d	RAB = 100 kΩ, frequency > 10 kHz, d = pulse duty factor	14
Pulsed terminal current IA, IW, IB, RAB = 10 kΩ, frequency ≤ 10 kHz	IA, IW, IB	-6		6	mA/√d	RAB = 10 kΩ, frequency ≤ 10 kHz, d = pulse duty factor	14
Pulsed terminal current IA, IW, IB, RAB = 100 kΩ, frequency ≤ 10 kHz	IA, IW, IB	-1.5		1.5	mA/√d	RAB = 100 kΩ, frequency ≤ 10 kHz, d = pulse duty factor	14
Digital Inputs		-0.3		7	V	VLOGIC + 0.3 V or +7 V, whichever is less	14
Operating Temperature Range	TA	-40		125	°C	Includes programming of EEPROM memory	14
Maximum Junction Temperature	TJ			150	°C		14
Storage Temperature Range		-65		150	°C		14
Reflow Soldering Peak Temperature				260	°C		14
Thermal Resistance, junction to ambient, 20-Lead TSSOP	θJA		105.92		°C/W	JEDEC 2S2P test board, still air (0 m/sec airflow)	14
Thermal Resistance, junction to board, 20-Lead TSSOP	θJB		51.78		°C/W		14
End-to-end nominal resistance, RAB (100 kΩ variant)	RAB		100		kΩ		36
Resistance Temperature Coefficient	(ΔRAB/RAB)/ΔT × 10^6		35		ppm/°C	Code = full scale	7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		EPAD Exposed Pad. Connect the exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plane	17

CAD (KiCad official)

Symbol: AD5144BRUZ100
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: ad5144bruz100-etched.step / ad5144bruz100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5144bruz100.step / ad5144bruz100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (37 pp, sha256 1b81c445bc598af2, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5144BRUZ100

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3D Model

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