component
AD5144BRUZ10-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAD5144BRUZ10-RL7
Analog Devices · Digital Potentiometers · TSSOP-20
AD5144BRUZ10-RL7 from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Synchronization data input, active low; data is loaded into the input shift register when SYNC returns high. |
| 2 | GND | power_in | Ground pin serving as the logic ground reference. |
| 3 | A1 | passive | Terminal A of RDAC1, with VSS ≤ VA ≤ VDD. |
| 4 | W1 | passive | Wiper terminal of RDAC1, with VSS ≤ VW ≤ VDD. |
| 5 | B1 | passive | Terminal B of RDAC1, with VSS ≤ VB ≤ VDD. |
| 6 | A3 | passive | Terminal A of RDAC3, with VSS ≤ VA ≤ VDD. |
| 7 | W3 | passive | Wiper terminal of RDAC3, with VSS ≤ VW ≤ VDD. |
| 8 | B3 | passive | Terminal B of RDAC3, with VSS ≤ VB ≤ VDD. |
| 9 | VSS | power_in | Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 10 | A2 | passive | Terminal A of RDAC2, with VSS ≤ VA ≤ VDD. |
| 11 | W2 | passive | Wiper terminal of RDAC2, with VSS ≤ VW ≤ VDD. |
| 12 | B2 | passive | Terminal B of RDAC2, with VSS ≤ VB ≤ VDD. |
| 13 | A4 | passive | Terminal A of RDAC4, with VSS ≤ VA ≤ VDD. |
| 14 | W4 | passive | Wiper terminal of RDAC4, with VSS ≤ VW ≤ VDD. |
| 15 | B4 | passive | Terminal B of RDAC4, with VSS ≤ VB ≤ VDD. |
| 16 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 17 | VLOGIC | power_in | Logic power supply from 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 18 | SCLK | input | Serial clock line; data is clocked in at the logic low transition. |
| 19 | SDI | input | Serial data input. |
| 20 | SDO | output | Serial data output; open-drain output that needs an external pull-up resistor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-20 |
| Category | ADC/DAC/Data Conversion |
| Pins | 20 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | EPAD Exposed Pad. Connect the exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plane | 17 |
CAD (KiCad official)
- Symbol:
AD5144BRUZ10-RL7 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
ad5144bruz10-rl7-etched.step/ad5144bruz10-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5144bruz10-rl7.step/ad5144bruz10-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (37 pp, sha256
1b81c445bc598af2, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).