component

AD5142BRUZ10-RL7

Public Made by Adom

by adom

Analog Devices Digital Potentiometers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5142bruz10-rl7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ad5142bruz10-rl7 / README.md
History Download
Ray Publish 0.1.0 957c6eb 5d ago

AD5142BRUZ10-RL7

Analog Devices · Digital Potentiometers · TSSOP-16

AD5142BRUZ10-RL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INDEP input Linear gain setting mode at power-up: each string resistor is loaded independently from its associated memory location, and once enabled it cannot be disabled by software.
2 RESET input Active-low hardware reset that refreshes the RDAC registers from EEPROM; tie to VLOGIC if the pin is not used.
3 GND power_in Ground pin serving as the logic ground reference.
4 A1 passive Terminal A of RDAC1, with VSS ≤ VA ≤ VDD.
5 W1 passive Wiper terminal of RDAC1, with VSS ≤ VW ≤ VDD.
6 B1 passive Terminal B of RDAC1, with VSS ≤ VB ≤ VDD.
7 VSS power_in Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors.
8 A2 passive Terminal A of RDAC2, with VSS ≤ VA ≤ VDD.
9 W2 passive Wiper terminal of RDAC2, with VSS ≤ VW ≤ VDD.
10 B2 passive Terminal B of RDAC2, with VSS ≤ VB ≤ VDD.
11 VDD power_in Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors.
12 VLOGIC power_in Logic power supply from 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors.
13 SCLK input Serial clock line; data is clocked in on the logic low transition.
14 SDI input Serial data input.
15 SDO output Serial data output; open-drain, so it requires an external pull-up resistor.
16 SYNC input Active-low synchronization input; data is loaded into the input shift register when SYNC returns high.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal Resistor Tolerance ΔRAB/RAB -8 1 8 % 5
Resistor Integral Nonlinearity (R-INL) R-INL -2 0.2 2 LSB RAB = 10 kΩ, VDD ≥ 2.7 V 5
Resistor Integral Nonlinearity (R-INL) R-INL -5 1.5 5 LSB RAB = 10 kΩ, VDD < 2.7 V 5
Resistor Differential Nonlinearity (R-DNL) R-DNL -0.5 0.2 0.5 LSB 5
Wiper Resistance RW 55 125 Ω Code = zero scale, RAB = 10 kΩ 5
Bottom Scale or Top Scale Resistance RBS or RTS 40 80 Ω RAB = 10 kΩ 5
Nominal Resistance Match RAB1/RAB2 -1 0.2 1 % Code = 0xFF 5
Integral Nonlinearity (INL) INL -1 0.2 1 LSB RAB = 10 kΩ 6
Differential Nonlinearity (DNL) DNL -0.5 0.2 0.5 LSB 6
Full-Scale Error VWFSE -2.5 -0.1 LSB RAB = 10 kΩ 6
Zero-Scale Error VWZSE 1.2 3 LSB RAB = 10 kΩ 6
Voltage Divider Temperature Coefficient (ΔVW/VW)/ΔT × 10^6 -5 5 ppm/°C Code = half scale 6
Maximum Continuous Current IA, IB, IW -6 6 mA RAB = 10 kΩ 6
Common-Mode Leakage Current -500 15 500 nA VA = VW = VB 6
Input Current IIN -1 1 µA 6
Output Low Voltage VOL 0.4 V ISINK = 3 mA 6
Output Low Voltage VOL 0.6 V ISINK = 6 mA, VLOGIC > 2.3 V 6
Three-State Leakage Current -1 1 µA 6
Single-Supply Power Range VDD 2.3 5.5 V VSS = GND 6
Dual-Supply Power Range 2.25 2.75 V 6
Logic Supply Range VLOGIC 1.8 V Single supply, VSS = GND 6
Logic Supply Range VLOGIC 2.25 V Dual supply, VSS < GND 6
Positive Supply Current IDD 0.7 5.5 µA VIH = VLOGIC or VIL = GND, VDD = 5.5 V 6
Negative Supply Current ISS -5.5 -0.7 µA VIH = VLOGIC or VIL = GND 7
Logic Supply Current ILOGIC 0.05 1.4 µA VIH = VLOGIC or VIL = GND 7
Power Supply Rejection Ratio PSRR -66 -60 dB ΔVDD/ΔVSS = VDD ± 10%, code = full scale 7
Endurance 1 Mcycles TA = 25°C 7
Endurance 100 kcycles 7
Data Retention 50 Years 7
VDD to GND VDD -0.3 7 V VDD to GND 10
VSS to GND VSS -7 0.3 V VSS to GND 10
VDD to VSS VDD − VSS 7 V 10
VLOGIC to GND VLOGIC -0.3 V Whichever is less of VDD + 0.3 V or +7.0 V 10
Digital Inputs -0.3 V Whichever is less of VLOGIC + 0.3 V or +7 V 10
Operating Temperature Range TA -40 125 °C 10
Maximum Junction Temperature TJ 150 °C Includes programming of EEPROM memory 10
Storage Temperature Range -65 150 °C 10
Reflow Soldering Peak Temperature 260 °C Reflow soldering 10
Time at Peak Temperature 20 40 sec At peak reflow temperature 10
Positive Supply Voltage (single supply) VDD 2.3 5.5 V VSS = 0 V 3
Logic Supply Voltage VLOGIC 1.8 5.5 V 3
Operating Temperature TA -40 125 °C −40°C < TA < +125°C 3
Nominal End-to-End Resistance (10 kΩ option) RAB 10 kΩ 26
Resistance Temperature Coefficient (ΔRAB/RAB)/ΔT × 10^6 35 ppm/°C Code = full scale 5
Thermal Resistance, Junction-to-Ambient (16-Lead TSSOP) θJA 134.43 °C/W JEDEC 2S2P thermal test board (simulated) 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plan 11

CAD (KiCad official)

  • Symbol: AD5142BRUZ10-RL7
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad5142bruz10-rl7-etched.step / ad5142bruz10-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5142bruz10-rl7.step / ad5142bruz10-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (27 pp, sha256 5cd9d7ed6a4c5f65, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF