component
AD5122ABCPZ100-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5122ABCPZ100-RL7
Analog Devices · Digital Potentiometers · LFCSP-16(3x3)
AD5122ABCPZ100-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin, logic ground reference. |
| 2 | A1 | passive | Terminal A of RDAC1; VSS ≤ VA ≤ VDD. |
| 3 | W1 | passive | Wiper terminal of RDAC1; VSS ≤ VW ≤ VDD. |
| 4 | B1 | passive | Terminal B of RDAC1; VSS ≤ VB ≤ VDD. |
| 5 | VSS | power_in | Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 6 | A2 | passive | Terminal A of RDAC2; VSS ≤ VA ≤ VDD. |
| 7 | W2 | passive | Wiper terminal of RDAC2; VSS ≤ VW ≤ VDD. |
| 8 | B2 | passive | Terminal B of RDAC2; VSS ≤ VB ≤ VDD. |
| 9 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 10 | VLOGIC | power_in | Logic power supply; 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 11 | SCL | input | Serial clock line of the I2C interface. |
| 12 | SDA | bidirectional | Serial data input/output of the I2C interface. |
| 13 | ADDR1 | input | Programmable address pin (ADDR1) for multiple package decoding. |
| 14 | ADDR0 | input | Programmable address pin (ADDR0) for multiple package decoding. |
| 15 | INDEP | input | Linear gain setting mode at power-up; each string resistor is loaded from its associated memory location, and once enabled it cannot be disabled by software. |
| 16 | RESET | input | Hardware reset pin that refreshes the RDAC registers from EEPROM when active low; tie to VLOGIC if not used. |
| 17 | EPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | Data Acquisition |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Integral Nonlinearity (R-INL), RAB = 100 kΩ | R-INL | -0.5 | 0.1 | 0.5 | LSB | RAB = 100 kΩ, VDD ≥ 2.7 V | 3 |
| Resistor Integral Nonlinearity (R-INL), RAB = 100 kΩ | R-INL | -1 | 0.25 | 1 | LSB | RAB = 100 kΩ, VDD < 2.7 V | 3 |
| Resistor Differential Nonlinearity (R-DNL) | R-DNL | -0.5 | 0.1 | 0.5 | LSB | 3 | |
| Nominal Resistor Tolerance | ΔRAB/RAB | -8 | 1 | 8 | % | 3 | |
| Nominal Resistance Match | RAB1/RAB2 | -1 | 0.2 | 1 | % | Code = 0xFF | 3 |
| Wiper Resistance | RW | 130 | 400 | Ω | Code = zero scale, RAB = 100 kΩ | 3 | |
| Bottom Scale or Top Scale Wiper Resistance | RBS or RTS | 60 | 230 | Ω | Bottom scale or top scale, RAB = 100 kΩ | 3 | |
| Integral Nonlinearity (INL), potentiometer divider | INL | -0.25 | 0.1 | 0.25 | LSB | RAB = 100 kΩ | 3 |
| Differential Nonlinearity (DNL), potentiometer divider | DNL | -0.25 | 0.1 | 0.25 | LSB | 3 | |
| Full-Scale Error | VWFSE | -0.5 | 0.1 | 0.5 | LSB | RAB = 100 kΩ | 3 |
| Zero-Scale Error | VWZSE | 0.25 | 0.5 | LSB | RAB = 100 kΩ | 3 | |
| Voltage Divider Temperature Coefficient | (ΔVW/VW)/ΔT × 106 | -5 | 5 | ppm/°C | Code = half scale | 3 | |
| Maximum Continuous Current IA, IB, IW | IA, IB, IW | -1.5 | 1.5 | mA | RAB = 100 kΩ | 4 | |
| Common-Mode Leakage Current | -500 | 15 | 500 | nA | VA = VW = VB | 4 | |
| Input Current | IIN | -1 | 1 | µA | 4 | ||
| Three-State Leakage Current | -1 | 1 | µA | 4 | |||
| Single-Supply Power Range | 2.3 | 5.5 | V | VSS = GND | 4 | ||
| Dual-Supply Power Range | 2.25 | 2.75 | V | Dual supply, ± | 4 | ||
| Logic Supply Range, single supply | 1.8 | V | Single supply, VSS = GND; upper limit VDD | 4 | |||
| Logic Supply Range, dual supply | 2.25 | V | Dual supply, VSS < GND; upper limit VDD | 4 | |||
| Positive Supply Current | IDD | 0.7 | 5.5 | µA | VIH = VLOGIC or VIL = GND, VDD = 5.5 V | 4 | |
| Negative Supply Current | ISS | -5.5 | -0.7 | µA | VIH = VLOGIC or VIL = GND | 4 | |
| Logic Supply Current | ILOGIC | 0.05 | 1.4 | µA | VIH = VLOGIC or VIL = GND | 4 | |
| Power Supply Rejection Ratio | PSRR | -66 | -60 | dB | ∆VDD/∆VSS = VDD ± 10%, code = full scale | 4 | |
| Maximum VDD to GND | -0.3 | 7 | V | VDD to GND | 11 | ||
| Maximum VSS to GND | -7 | 0.3 | V | VSS to GND | 11 | ||
| Maximum VDD to VSS | 7 | V | VDD to VSS | 11 | |||
| VLOGIC to GND | -0.3 | V | Upper limit: VDD + 0.3 V or +7.0 V, whichever is less | 11 | |||
| Digital Inputs voltage | -0.3 | V | Upper limit: VLOGIC + 0.3 V or +7 V, whichever is less | 11 | |||
| IA, IW, IB pulsed current, RAB = 100 kΩ | -1.5 | 1.5 | mA/d | RAB = 100 kΩ, pulsed, frequency > 10 kHz; d = pulse duty factor | 11 | ||
| IA, IW, IB pulsed current, RAB = 100 kΩ | -1.5 | 1.5 | mA/√d | RAB = 100 kΩ, pulsed, frequency ≤ 10 kHz; d = pulse duty factor | 11 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Includes programming of EEPROM memory | 11 | |
| Maximum Junction Temperature | TJ | 150 | °C | 11 | |||
| Storage Temperature Range | -65 | 150 | °C | 11 | |||
| Reflow Soldering Peak Temperature | 260 | °C | Reflow soldering | 11 | |||
| Time at Peak Temperature | 20 | 40 | sec | Time at peak temperature (reflow) | 11 | ||
| FICDM ESD rating | 1.5 | kV | FICDM | 11 | |||
| Supply Voltage VDD (recommended) | VDD | 2.3 | 5.5 | V | Single supply, VSS = 0 V | 3 | |
| Logic Supply Voltage VLOGIC (recommended) | VLOGIC | 1.8 | 5.5 | V | Upper limit VDD | 3 | |
| Operating Temperature (recommended) | TA | -40 | 125 | °C | −40°C < TA < +125°C | 3 | |
| Thermal Resistance Junction-to-Ambient, 16-Lead LFCSP | θJA | 89.51 | °C/W | JEDEC 2S2P test board, still air (0 m/sec airflow) | 11 | ||
| Thermal Resistance Junction-to-Case, 16-Lead LFCSP | θJC | 3 | °C/W | 16-Lead LFCSP | 11 | ||
| Resistance Temperature Coefficient | (ΔRAB/RAB)/ΔT × 106 | 35 | ppm/°C | Code = full scale | 3 | ||
| End-to-End Resistance RAB (nominal) | RAB | 100 | kΩ | Nominal, AD5122ABCPZ100-RL7 per ordering guide | 29 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plan | 12 |
CAD (KiCad official)
- Symbol:
AD5122ABCPZ100-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5122abcpz100-rl7-etched.step/ad5122abcpz100-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5122abcpz100-rl7.step/ad5122abcpz100-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
abe9f20a6a11b02e, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5122ABCPZ100-RL7
**Analog Devices** · Digital Potentiometers · LFCSP-16(3x3)
AD5122ABCPZ100-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin, logic ground reference. |
| 2 | A1 | passive | Terminal A of RDAC1; VSS ≤ VA ≤ VDD. |
| 3 | W1 | passive | Wiper terminal of RDAC1; VSS ≤ VW ≤ VDD. |
| 4 | B1 | passive | Terminal B of RDAC1; VSS ≤ VB ≤ VDD. |
| 5 | VSS | power_in | Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 6 | A2 | passive | Terminal A of RDAC2; VSS ≤ VA ≤ VDD. |
| 7 | W2 | passive | Wiper terminal of RDAC2; VSS ≤ VW ≤ VDD. |
| 8 | B2 | passive | Terminal B of RDAC2; VSS ≤ VB ≤ VDD. |
| 9 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 10 | VLOGIC | power_in | Logic power supply; 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 11 | SCL | input | Serial clock line of the I2C interface. |
| 12 | SDA | bidirectional | Serial data input/output of the I2C interface. |
| 13 | ADDR1 | input | Programmable address pin (ADDR1) for multiple package decoding. |
| 14 | ADDR0 | input | Programmable address pin (ADDR0) for multiple package decoding. |
| 15 | INDEP | input | Linear gain setting mode at power-up; each string resistor is loaded from its associated memory location, and once enabled it cannot be disabled by software. |
| 16 | RESET | input | Hardware reset pin that refreshes the RDAC registers from EEPROM when active low; tie to VLOGIC if not used. |
| 17 | EPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | Data Acquisition |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Resistor Integral Nonlinearity (R-INL), RAB = 100 kΩ | R-INL | -0.5 | 0.1 | 0.5 | LSB | RAB = 100 kΩ, VDD ≥ 2.7 V | 3 |
| Resistor Integral Nonlinearity (R-INL), RAB = 100 kΩ | R-INL | -1 | 0.25 | 1 | LSB | RAB = 100 kΩ, VDD < 2.7 V | 3 |
| Resistor Differential Nonlinearity (R-DNL) | R-DNL | -0.5 | 0.1 | 0.5 | LSB | | 3 |
| Nominal Resistor Tolerance | ΔRAB/RAB | -8 | 1 | 8 | % | | 3 |
| Nominal Resistance Match | RAB1/RAB2 | -1 | 0.2 | 1 | % | Code = 0xFF | 3 |
| Wiper Resistance | RW | | 130 | 400 | Ω | Code = zero scale, RAB = 100 kΩ | 3 |
| Bottom Scale or Top Scale Wiper Resistance | RBS or RTS | | 60 | 230 | Ω | Bottom scale or top scale, RAB = 100 kΩ | 3 |
| Integral Nonlinearity (INL), potentiometer divider | INL | -0.25 | 0.1 | 0.25 | LSB | RAB = 100 kΩ | 3 |
| Differential Nonlinearity (DNL), potentiometer divider | DNL | -0.25 | 0.1 | 0.25 | LSB | | 3 |
| Full-Scale Error | VWFSE | -0.5 | 0.1 | 0.5 | LSB | RAB = 100 kΩ | 3 |
| Zero-Scale Error | VWZSE | | 0.25 | 0.5 | LSB | RAB = 100 kΩ | 3 |
| Voltage Divider Temperature Coefficient | (ΔVW/VW)/ΔT × 106 | -5 | | 5 | ppm/°C | Code = half scale | 3 |
| Maximum Continuous Current IA, IB, IW | IA, IB, IW | -1.5 | | 1.5 | mA | RAB = 100 kΩ | 4 |
| Common-Mode Leakage Current | | -500 | 15 | 500 | nA | VA = VW = VB | 4 |
| Input Current | IIN | -1 | | 1 | µA | | 4 |
| Three-State Leakage Current | | -1 | | 1 | µA | | 4 |
| Single-Supply Power Range | | 2.3 | | 5.5 | V | VSS = GND | 4 |
| Dual-Supply Power Range | | 2.25 | | 2.75 | V | Dual supply, ± | 4 |
| Logic Supply Range, single supply | | 1.8 | | | V | Single supply, VSS = GND; upper limit VDD | 4 |
| Logic Supply Range, dual supply | | 2.25 | | | V | Dual supply, VSS < GND; upper limit VDD | 4 |
| Positive Supply Current | IDD | | 0.7 | 5.5 | µA | VIH = VLOGIC or VIL = GND, VDD = 5.5 V | 4 |
| Negative Supply Current | ISS | -5.5 | | -0.7 | µA | VIH = VLOGIC or VIL = GND | 4 |
| Logic Supply Current | ILOGIC | | 0.05 | 1.4 | µA | VIH = VLOGIC or VIL = GND | 4 |
| Power Supply Rejection Ratio | PSRR | | -66 | -60 | dB | ∆VDD/∆VSS = VDD ± 10%, code = full scale | 4 |
| Maximum VDD to GND | | -0.3 | | 7 | V | VDD to GND | 11 |
| Maximum VSS to GND | | -7 | | 0.3 | V | VSS to GND | 11 |
| Maximum VDD to VSS | | | | 7 | V | VDD to VSS | 11 |
| VLOGIC to GND | | -0.3 | | | V | Upper limit: VDD + 0.3 V or +7.0 V, whichever is less | 11 |
| Digital Inputs voltage | | -0.3 | | | V | Upper limit: VLOGIC + 0.3 V or +7 V, whichever is less | 11 |
| IA, IW, IB pulsed current, RAB = 100 kΩ | | -1.5 | | 1.5 | mA/d | RAB = 100 kΩ, pulsed, frequency > 10 kHz; d = pulse duty factor | 11 |
| IA, IW, IB pulsed current, RAB = 100 kΩ | | -1.5 | | 1.5 | mA/√d | RAB = 100 kΩ, pulsed, frequency ≤ 10 kHz; d = pulse duty factor | 11 |
| Operating Temperature Range | TA | -40 | | 125 | °C | Includes programming of EEPROM memory | 11 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 11 |
| Storage Temperature Range | | -65 | | 150 | °C | | 11 |
| Reflow Soldering Peak Temperature | | | | 260 | °C | Reflow soldering | 11 |
| Time at Peak Temperature | | 20 | | 40 | sec | Time at peak temperature (reflow) | 11 |
| FICDM ESD rating | | | | 1.5 | kV | FICDM | 11 |
| Supply Voltage VDD (recommended) | VDD | 2.3 | | 5.5 | V | Single supply, VSS = 0 V | 3 |
| Logic Supply Voltage VLOGIC (recommended) | VLOGIC | 1.8 | | 5.5 | V | Upper limit VDD | 3 |
| Operating Temperature (recommended) | TA | -40 | | 125 | °C | −40°C < TA < +125°C | 3 |
| Thermal Resistance Junction-to-Ambient, 16-Lead LFCSP | θJA | | 89.51 | | °C/W | JEDEC 2S2P test board, still air (0 m/sec airflow) | 11 |
| Thermal Resistance Junction-to-Case, 16-Lead LFCSP | θJC | | 3 | | °C/W | 16-Lead LFCSP | 11 |
| Resistance Temperature Coefficient | (ΔRAB/RAB)/ΔT × 106 | | 35 | | ppm/°C | Code = full scale | 3 |
| End-to-End Resistance RAB (nominal) | RAB | | 100 | | kΩ | Nominal, AD5122ABCPZ100-RL7 per ordering guide | 29 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plan | 12 |
## CAD (KiCad official)
- Symbol: `AD5122ABCPZ100-RL7`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `ad5122abcpz100-rl7-etched.step` / `ad5122abcpz100-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5122abcpz100-rl7.step` / `ad5122abcpz100-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589802337335750656) (32 pp, sha256 `abe9f20a6a11b02e`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5122abcpz100-rl7-datasheet.pdf)